From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtpbg153.qq.com (smtpbg153.qq.com [13.245.218.24]) by sourceware.org (Postfix) with ESMTPS id 0D7FA3858439 for ; Tue, 16 May 2023 10:21:49 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 0D7FA3858439 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp68t1684232503tm04d8c4 Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 16 May 2023 18:21:42 +0800 (CST) X-QQ-SSF: 01400000000000F0R000000A0000000 X-QQ-FEAT: WVlUXBcs7uRubUITGUryodZKi8nc6appiNdWm9e9/UkvDLQh/Jjo0woGbPfOw J4Fi9iTLWZeKfdx+GeODBQuWvgCdrPE0J72eGCHace0cP/EJ/U9iIwmdGMzN92xxn8GDZtB y4Jg74Ieh6pb/b/kzTKDIBU7QTVxnuag8xVECgtDO7WI0DGgsekg0CFh+ArfgI2SyVPowBI sEMi3fazylfmi8jiGxhjTFX1R33v8vfDUI5mXhrWqj4Dcr788qkUCeEcEUnhg1ISqvcsKJ3 66SLflsQbjBisaMXJYgzxARKfE6wy+2D+1Zkarf9KyYA/7hv7n7xFylxTbakHYkLZAArdLT ErOsIDKLnYFkpC3AiHcbw2nfygD5y32KBJoC/QhD1si7hG1VfKZxvMQx2cy2xezZ0ln/yOs 7pTwEugUGL0= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 12978473028483452871 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: richard.sandiford@arm.com, rguenther@suse.de, Juzhe-Zhong Subject: [PATCH V2] RISC-V: Add FRM and rounding mode operand into floating point intrinsics Date: Tue, 16 May 2023 18:21:24 +0800 Message-Id: <20230516102124.2896235-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Juzhe-Zhong This patch is adding rounding mode operand and FRM_REGNUM dependency into floating-point instructions. The floating-point instructions we added FRM and rounding mode operand: 1. vfadd/vfsub 2. vfwadd/vfwsub 3. vfmul 4. vfdiv 5. vfwmul 6. vfwmacc/vfwnmacc/vfwmsac/vfwnmsac 7. vfsqrt 8. floating-point conversions. 9. floating-point reductions. 10. floating-point ternary. The floating-point instructions we did NOT add FRM and rounding mode operand: 1. vfabs/vfneg/vfsqrt7/vfrec7 2. vfmin/vfmax 3. comparisons 4. vfclass 5. vfsgnj/vfsgnjn/vfsgnjx 6. vfmerge 7. vfmv.v.f gcc/ChangeLog: * config/riscv/riscv-protos.h (enum frm_field_enum): New enum. * config/riscv/riscv-vector-builtins.cc (function_expander::use_ternop_insn): Add default rounding mode. (function_expander::use_widen_ternop_insn): Ditto. * config/riscv/riscv.cc (riscv_hard_regno_nregs): Add FRM REGNUM. (riscv_hard_regno_mode_ok): Ditto. (riscv_conditional_register_usage): Ditto. * config/riscv/riscv.h (DWARF_FRAME_REGNUM): Ditto. (FRM_REG_P): Ditto. (RISCV_DWARF_FRM): Ditto. * config/riscv/riscv.md: Ditto. * config/riscv/vector-iterators.md: split no frm and has frm operations. * config/riscv/vector.md (@pred__scalar): New pattern. (@pred_): Ditto. --- gcc/config/riscv/riscv-protos.h | 10 + gcc/config/riscv/riscv-vector-builtins.cc | 14 ++ gcc/config/riscv/riscv.cc | 7 +- gcc/config/riscv/riscv.h | 7 +- gcc/config/riscv/riscv.md | 1 + gcc/config/riscv/vector-iterators.md | 9 +- gcc/config/riscv/vector.md | 258 ++++++++++++++++++---- 7 files changed, 251 insertions(+), 55 deletions(-) diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 835bb802fc6..12634d0ac1a 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -231,6 +231,16 @@ enum vxrm_field_enum VXRM_RDN, VXRM_ROD }; +/* Rounding mode bitfield for floating point FRM. */ +enum frm_field_enum +{ + FRM_RNE = 0b000, + FRM_RTZ = 0b001, + FRM_RDN = 0b010, + FRM_RUP = 0b011, + FRM_RMM = 0b100, + DYN = 0b111 +}; } /* We classify builtin types into two classes: diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc index 1de075fb90d..b7458aaace6 100644 --- a/gcc/config/riscv/riscv-vector-builtins.cc +++ b/gcc/config/riscv/riscv-vector-builtins.cc @@ -3460,6 +3460,13 @@ function_expander::use_ternop_insn (bool vd_accum_p, insn_code icode) add_input_operand (Pmode, get_tail_policy_for_pred (pred)); add_input_operand (Pmode, get_mask_policy_for_pred (pred)); add_input_operand (Pmode, get_avl_type_rtx (avl_type::NONVLMAX)); + + /* TODO: Currently, we don't support intrinsic that is modeling rounding mode. + We add default rounding mode for the intrinsics that didn't model rounding + mode yet. */ + if (opno != insn_data[icode].n_generator_args) + add_input_operand (Pmode, const0_rtx); + return generate_insn (icode); } @@ -3482,6 +3489,13 @@ function_expander::use_widen_ternop_insn (insn_code icode) add_input_operand (Pmode, get_tail_policy_for_pred (pred)); add_input_operand (Pmode, get_mask_policy_for_pred (pred)); add_input_operand (Pmode, get_avl_type_rtx (avl_type::NONVLMAX)); + + /* TODO: Currently, we don't support intrinsic that is modeling rounding mode. + We add default rounding mode for the intrinsics that didn't model rounding + mode yet. */ + if (opno != insn_data[icode].n_generator_args) + add_input_operand (Pmode, const0_rtx); + return generate_insn (icode); } diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index b52e613c629..de5b87b1a87 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -6082,7 +6082,8 @@ riscv_hard_regno_nregs (unsigned int regno, machine_mode mode) /* mode for VL or VTYPE are just a marker, not holding value, so it always consume one register. */ - if (VTYPE_REG_P (regno) || VL_REG_P (regno) || VXRM_REG_P (regno)) + if (VTYPE_REG_P (regno) || VL_REG_P (regno) || VXRM_REG_P (regno) + || FRM_REG_P (regno)) return 1; /* Assume every valid non-vector mode fits in one vector register. */ @@ -6150,7 +6151,8 @@ riscv_hard_regno_mode_ok (unsigned int regno, machine_mode mode) if (lmul != 1) return ((regno % lmul) == 0); } - else if (VTYPE_REG_P (regno) || VL_REG_P (regno) || VXRM_REG_P (regno)) + else if (VTYPE_REG_P (regno) || VL_REG_P (regno) || VXRM_REG_P (regno) + || FRM_REG_P (regno)) return true; else return false; @@ -6587,6 +6589,7 @@ riscv_conditional_register_usage (void) fixed_regs[VTYPE_REGNUM] = call_used_regs[VTYPE_REGNUM] = 1; fixed_regs[VL_REGNUM] = call_used_regs[VL_REGNUM] = 1; fixed_regs[VXRM_REGNUM] = call_used_regs[VXRM_REGNUM] = 1; + fixed_regs[FRM_REGNUM] = call_used_regs[FRM_REGNUM] = 1; } } diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index f74b70de562..f55bd6112a8 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -121,8 +121,9 @@ ASM_MISA_SPEC /* The mapping from gcc register number to DWARF 2 CFA column number. */ #define DWARF_FRAME_REGNUM(REGNO) \ - (VXRM_REG_P (REGNO) ? RISCV_DWARF_VXRM \ - : VL_REG_P (REGNO) ? RISCV_DWARF_VL \ + (FRM_REG_P (REGNO) ? RISCV_DWARF_FRM \ + : VXRM_REG_P (REGNO) ? RISCV_DWARF_VXRM \ + : VL_REG_P (REGNO) ? RISCV_DWARF_VL \ : VTYPE_REG_P (REGNO) \ ? RISCV_DWARF_VTYPE \ : (GP_REG_P (REGNO) || FP_REG_P (REGNO) || V_REG_P (REGNO) \ @@ -374,6 +375,7 @@ ASM_MISA_SPEC #define VL_REG_P(REGNO) ((REGNO) == VL_REGNUM) #define VTYPE_REG_P(REGNO) ((REGNO) == VTYPE_REGNUM) #define VXRM_REG_P(REGNO) ((REGNO) == VXRM_REGNUM) +#define FRM_REG_P(REGNO) ((REGNO) == FRM_REGNUM) /* True when REGNO is in SIBCALL_REGS set. */ #define SIBCALL_REG_P(REGNO) \ @@ -392,6 +394,7 @@ ASM_MISA_SPEC #define FRAME_POINTER_REGNUM 65 /* Define Dwarf for RVV. */ +#define RISCV_DWARF_FRM (4096 + 0x003) #define RISCV_DWARF_VXRM (4096 + 0x00a) #define RISCV_DWARF_VL (4096 + 0xc20) #define RISCV_DWARF_VTYPE (4096 + 0xc21) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index c5cf3af9868..91808d6bd2a 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -136,6 +136,7 @@ (VL_REGNUM 66) (VTYPE_REGNUM 67) (VXRM_REGNUM 68) + (FRM_REGNUM 69) ]) (include "predicates.md") diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index a282861335d..3096ac5be3c 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -1436,10 +1436,13 @@ (define_code_iterator and_ior [and ior]) -(define_code_iterator any_float_binop [plus mult smax smin minus div]) -(define_code_iterator commutative_float_binop [plus mult smax smin]) +(define_code_iterator any_float_binop [plus mult minus div]) +(define_code_iterator any_float_binop_nofrm [smax smin]) +(define_code_iterator commutative_float_binop [plus mult]) +(define_code_iterator commutative_float_binop_nofrm [smax smin]) (define_code_iterator non_commutative_float_binop [minus div]) -(define_code_iterator any_float_unop [neg abs sqrt]) +(define_code_iterator any_float_unop [sqrt]) +(define_code_iterator any_float_unop_nofrm [neg abs]) (define_code_iterator any_fix [fix unsigned_fix]) (define_code_iterator any_float [float unsigned_float]) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index e0aeeea57a4..a06b84d7473 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -5722,8 +5722,10 @@ (match_operand 6 "const_int_operand" " i, i, i, i") (match_operand 7 "const_int_operand" " i, i, i, i") (match_operand 8 "const_int_operand" " i, i, i, i") + (match_operand 9 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (any_float_binop:VF (match_operand:VF 3 "register_operand" " vr, vr, vr, vr") (match_operand:VF 4 "register_operand" " vr, vr, vr, vr")) @@ -5733,7 +5735,7 @@ [(set_attr "type" "") (set_attr "mode" "")]) -(define_insn "@pred__scalar" +(define_insn "@pred_" [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr") (if_then_else:VF (unspec: @@ -5744,6 +5746,28 @@ (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (any_float_binop_nofrm:VF + (match_operand:VF 3 "register_operand" " vr, vr, vr, vr") + (match_operand:VF 4 "register_operand" " vr, vr, vr, vr")) + (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] + "TARGET_VECTOR" + "vf.vv\t%0,%3,%4%p1" + [(set_attr "type" "") + (set_attr "mode" "")]) + +(define_insn "@pred__scalar" + [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr") + (if_then_else:VF + (unspec: + [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") + (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i") + (match_operand 9 "const_int_operand" " i, i, i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (commutative_float_binop:VF (vec_duplicate:VF (match_operand: 4 "register_operand" " f, f, f, f")) @@ -5765,6 +5789,29 @@ (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (commutative_float_binop_nofrm:VF + (vec_duplicate:VF + (match_operand: 4 "register_operand" " f, f, f, f")) + (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")) + (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] + "TARGET_VECTOR" + "vf.vf\t%0,%3,%4%p1" + [(set_attr "type" "") + (set_attr "mode" "")]) + +(define_insn "@pred__scalar" + [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr") + (if_then_else:VF + (unspec: + [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") + (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i") + (match_operand 9 "const_int_operand" " i, i, i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (non_commutative_float_binop:VF (match_operand:VF 3 "register_operand" " vr, vr, vr, vr") (vec_duplicate:VF @@ -5784,8 +5831,10 @@ (match_operand 6 "const_int_operand" " i, i, i, i") (match_operand 7 "const_int_operand" " i, i, i, i") (match_operand 8 "const_int_operand" " i, i, i, i") + (match_operand 9 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (non_commutative_float_binop:VF (vec_duplicate:VF (match_operand: 4 "register_operand" " f, f, f, f")) @@ -5853,8 +5902,10 @@ (match_operand 7 "const_int_operand") (match_operand 8 "const_int_operand") (match_operand 9 "const_int_operand") + (match_operand 10 "const_int_operand") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VF (mult:VF (match_operand:VF 2 "register_operand") @@ -5878,8 +5929,10 @@ (match_operand 6 "const_int_operand" " i, i, i, i") (match_operand 7 "const_int_operand" " i, i, i, i") (match_operand 8 "const_int_operand" " i, i, i, i") + (match_operand 9 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VF (mult:VF (match_operand:VF 2 "register_operand" " 0, vr, 0, vr") @@ -5909,8 +5962,10 @@ (match_operand 6 "const_int_operand" " i, i, i, i") (match_operand 7 "const_int_operand" " i, i, i, i") (match_operand 8 "const_int_operand" " i, i, i, i") + (match_operand 9 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VF (mult:VF (match_operand:VF 2 "register_operand" " vr, vr, vr, vr") @@ -5940,8 +5995,10 @@ (match_operand 7 "const_int_operand" " i, i") (match_operand 8 "const_int_operand" " i, i") (match_operand 9 "const_int_operand" " i, i") + (match_operand 10 "const_int_operand" " i, i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VF (mult:VF (match_operand:VF 2 "register_operand" " vr, vr") @@ -5975,8 +6032,10 @@ (match_operand 7 "const_int_operand") (match_operand 8 "const_int_operand") (match_operand 9 "const_int_operand") + (match_operand 10 "const_int_operand") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VF (mult:VF (vec_duplicate:VF @@ -5996,8 +6055,10 @@ (match_operand 6 "const_int_operand" " i, i, i, i") (match_operand 7 "const_int_operand" " i, i, i, i") (match_operand 8 "const_int_operand" " i, i, i, i") + (match_operand 9 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VF (mult:VF (vec_duplicate:VF @@ -6028,8 +6089,10 @@ (match_operand 6 "const_int_operand" " i, i, i, i") (match_operand 7 "const_int_operand" " i, i, i, i") (match_operand 8 "const_int_operand" " i, i, i, i") + (match_operand 9 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VF (mult:VF (vec_duplicate:VF @@ -6060,8 +6123,10 @@ (match_operand 7 "const_int_operand" " i, i") (match_operand 8 "const_int_operand" " i, i") (match_operand 9 "const_int_operand" " i, i") + (match_operand 10 "const_int_operand" " i, i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VF (mult:VF (vec_duplicate:VF @@ -6095,8 +6160,10 @@ (match_operand 7 "const_int_operand") (match_operand 8 "const_int_operand") (match_operand 9 "const_int_operand") + (match_operand 10 "const_int_operand") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VF (neg:VF (mult:VF @@ -6121,8 +6188,10 @@ (match_operand 6 "const_int_operand" " i, i, i, i") (match_operand 7 "const_int_operand" " i, i, i, i") (match_operand 8 "const_int_operand" " i, i, i, i") + (match_operand 9 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VF (neg:VF (mult:VF @@ -6153,8 +6222,10 @@ (match_operand 6 "const_int_operand" " i, i, i, i") (match_operand 7 "const_int_operand" " i, i, i, i") (match_operand 8 "const_int_operand" " i, i, i, i") + (match_operand 9 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VF (neg:VF (mult:VF @@ -6185,8 +6256,10 @@ (match_operand 7 "const_int_operand" " i, i") (match_operand 8 "const_int_operand" " i, i") (match_operand 9 "const_int_operand" " i, i") + (match_operand 10 "const_int_operand" " i, i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VF (neg:VF (mult:VF @@ -6221,8 +6294,10 @@ (match_operand 7 "const_int_operand") (match_operand 8 "const_int_operand") (match_operand 9 "const_int_operand") + (match_operand 10 "const_int_operand") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VF (neg:VF (mult:VF @@ -6243,8 +6318,10 @@ (match_operand 6 "const_int_operand" " i, i, i, i") (match_operand 7 "const_int_operand" " i, i, i, i") (match_operand 8 "const_int_operand" " i, i, i, i") + (match_operand 9 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VF (neg:VF (mult:VF @@ -6276,8 +6353,10 @@ (match_operand 6 "const_int_operand" " i, i, i, i") (match_operand 7 "const_int_operand" " i, i, i, i") (match_operand 8 "const_int_operand" " i, i, i, i") + (match_operand 9 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VF (neg:VF (mult:VF @@ -6309,8 +6388,10 @@ (match_operand 7 "const_int_operand" " i, i") (match_operand 8 "const_int_operand" " i, i") (match_operand 9 "const_int_operand" " i, i") + (match_operand 10 "const_int_operand" " i, i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VF (neg:VF (mult:VF @@ -6356,8 +6437,10 @@ (match_operand 5 "const_int_operand" " i, i, i, i") (match_operand 6 "const_int_operand" " i, i, i, i") (match_operand 7 "const_int_operand" " i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (any_float_unop:VF (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")) (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] @@ -6370,6 +6453,29 @@ (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])")) (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))]) +(define_insn "@pred_" + [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr") + (if_then_else:VF + (unspec: + [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") + (match_operand 4 "vector_length_operand" " rK, rK, rK, rK") + (match_operand 5 "const_int_operand" " i, i, i, i") + (match_operand 6 "const_int_operand" " i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (any_float_unop_nofrm:VF + (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")) + (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] + "TARGET_VECTOR" + "vf.v\t%0,%3%p1" + [(set_attr "type" "") + (set_attr "mode" "") + (set_attr "vl_op_idx" "4") + (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])")) + (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])")) + (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))]) + (define_insn "@pred_" [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr") (if_then_else:VF @@ -6426,8 +6532,10 @@ (match_operand 6 "const_int_operand" " i, i") (match_operand 7 "const_int_operand" " i, i") (match_operand 8 "const_int_operand" " i, i") + (match_operand 9 "const_int_operand" " i, i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (any_widen_binop:VWEXTF (float_extend:VWEXTF (match_operand: 3 "register_operand" " vr, vr")) @@ -6448,8 +6556,10 @@ (match_operand 6 "const_int_operand" " i, i") (match_operand 7 "const_int_operand" " i, i") (match_operand 8 "const_int_operand" " i, i") + (match_operand 9 "const_int_operand" " i, i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (any_widen_binop:VWEXTF (float_extend:VWEXTF (match_operand: 3 "register_operand" " vr, vr")) @@ -6471,8 +6581,10 @@ (match_operand 6 "const_int_operand" " i, i") (match_operand 7 "const_int_operand" " i, i") (match_operand 8 "const_int_operand" " i, i") + (match_operand 9 "const_int_operand" " i, i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VWEXTF (match_operand:VWEXTF 3 "register_operand" " vr, vr") (float_extend:VWEXTF @@ -6492,8 +6604,10 @@ (match_operand 6 "const_int_operand" " i, i") (match_operand 7 "const_int_operand" " i, i") (match_operand 8 "const_int_operand" " i, i") + (match_operand 9 "const_int_operand" " i, i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VWEXTF (match_operand:VWEXTF 3 "register_operand" " vr, vr") (float_extend:VWEXTF @@ -6521,8 +6635,10 @@ (match_operand 6 "const_int_operand" " i") (match_operand 7 "const_int_operand" " i") (match_operand 8 "const_int_operand" " i") + (match_operand 9 "const_int_operand" " i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VWEXTF (mult:VWEXTF (float_extend:VWEXTF @@ -6545,8 +6661,10 @@ (match_operand 6 "const_int_operand" " i") (match_operand 7 "const_int_operand" " i") (match_operand 8 "const_int_operand" " i") + (match_operand 9 "const_int_operand" " i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VWEXTF (mult:VWEXTF (float_extend:VWEXTF @@ -6570,8 +6688,10 @@ (match_operand 6 "const_int_operand" " i") (match_operand 7 "const_int_operand" " i") (match_operand 8 "const_int_operand" " i") + (match_operand 9 "const_int_operand" " i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VWEXTF (neg:VWEXTF (mult:VWEXTF @@ -6595,8 +6715,10 @@ (match_operand 6 "const_int_operand" " i") (match_operand 7 "const_int_operand" " i") (match_operand 8 "const_int_operand" " i") + (match_operand 9 "const_int_operand" " i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VWEXTF (neg:VWEXTF (mult:VWEXTF @@ -6910,8 +7032,10 @@ (match_operand 5 "const_int_operand" " i, i, i, i") (match_operand 6 "const_int_operand" " i, i, i, i") (match_operand 7 "const_int_operand" " i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (unspec: [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] VFCVTS) (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0")))] @@ -6929,8 +7053,10 @@ (match_operand 5 "const_int_operand" " i, i, i, i") (match_operand 6 "const_int_operand" " i, i, i, i") (match_operand 7 "const_int_operand" " i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (any_fix: (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")) (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0")))] @@ -6948,8 +7074,10 @@ (match_operand 5 "const_int_operand" " i, i, i, i") (match_operand 6 "const_int_operand" " i, i, i, i") (match_operand 7 "const_int_operand" " i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (any_float:VF (match_operand: 3 "register_operand" " vr, vr, vr, vr")) (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] @@ -6974,8 +7102,10 @@ (match_operand 5 "const_int_operand" " i, i") (match_operand 6 "const_int_operand" " i, i") (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (unspec:VWCONVERTI [(match_operand: 3 "register_operand" " vr, vr")] VFCVTS) (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0")))] @@ -6993,8 +7123,10 @@ (match_operand 5 "const_int_operand" " i, i") (match_operand 6 "const_int_operand" " i, i") (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (any_fix:VWCONVERTI (match_operand: 3 "register_operand" " vr, vr")) (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0")))] @@ -7012,8 +7144,10 @@ (match_operand 5 "const_int_operand" " i, i") (match_operand 6 "const_int_operand" " i, i") (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (any_float:VF (match_operand: 3 "register_operand" " vr, vr")) (match_operand:VF 2 "vector_merge_operand" " vu, 0")))] @@ -7031,8 +7165,10 @@ (match_operand 5 "const_int_operand" " i, i") (match_operand 6 "const_int_operand" " i, i") (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (float_extend:VWEXTF (match_operand: 3 "register_operand" " vr, vr")) (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))] @@ -7057,8 +7193,10 @@ (match_operand 5 "const_int_operand" " i, i, i, i, i, i") (match_operand 6 "const_int_operand" " i, i, i, i, i, i") (match_operand 7 "const_int_operand" " i, i, i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i, i, i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (unspec: [(match_operand:VF 3 "register_operand" " 0, 0, 0, 0, vr, vr")] VFCVTS) (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))] @@ -7076,8 +7214,10 @@ (match_operand 5 "const_int_operand" " i, i, i, i, i, i") (match_operand 6 "const_int_operand" " i, i, i, i, i, i") (match_operand 7 "const_int_operand" " i, i, i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i, i, i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (any_fix: (match_operand:VF 3 "register_operand" " 0, 0, 0, 0, vr, vr")) (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))] @@ -7095,8 +7235,10 @@ (match_operand 5 "const_int_operand" " i, i, i, i, i, i") (match_operand 6 "const_int_operand" " i, i, i, i, i, i") (match_operand 7 "const_int_operand" " i, i, i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i, i, i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (any_float: (match_operand:VWCONVERTI 3 "register_operand" " 0, 0, 0, 0, vr, vr")) (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))] @@ -7114,8 +7256,10 @@ (match_operand 5 "const_int_operand" " i, i, i, i, i, i") (match_operand 6 "const_int_operand" " i, i, i, i, i, i") (match_operand 7 "const_int_operand" " i, i, i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i, i, i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (float_truncate: (match_operand:VWEXTF 3 "register_operand" " 0, 0, 0, 0, vr, vr")) (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))] @@ -7133,8 +7277,10 @@ (match_operand 5 "const_int_operand" " i, i, i, i, i, i") (match_operand 6 "const_int_operand" " i, i, i, i, i, i") (match_operand 7 "const_int_operand" " i, i, i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i, i, i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (unspec: [(float_truncate: (match_operand:VWEXTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))] UNSPEC_ROD) @@ -7289,8 +7435,10 @@ (match_operand 5 "vector_length_operand" " rK, rK") (match_operand 6 "const_int_operand" " i, i") (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (any_freduc:VF (vec_duplicate:VF (vec_select: @@ -7311,8 +7459,10 @@ (match_operand 5 "vector_length_operand" " rK, rK") (match_operand 6 "const_int_operand" " i, i") (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (any_freduc:VF_ZVE64 (vec_duplicate:VF_ZVE64 (vec_select: @@ -7333,8 +7483,10 @@ (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") (match_operand 6 "const_int_operand" " i, i, i, i") (match_operand 7 "const_int_operand" " i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (any_freduc:VF_ZVE32 (vec_duplicate:VF_ZVE32 (vec_select: @@ -7356,8 +7508,10 @@ (match_operand 5 "vector_length_operand" " rK, rK") (match_operand 6 "const_int_operand" " i, i") (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (plus:VF (vec_duplicate:VF (vec_select: @@ -7379,8 +7533,10 @@ (match_operand 5 "vector_length_operand" " rK, rK") (match_operand 6 "const_int_operand" " i, i") (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (plus:VF_ZVE64 (vec_duplicate:VF_ZVE64 (vec_select: @@ -7402,8 +7558,10 @@ (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") (match_operand 6 "const_int_operand" " i, i, i, i") (match_operand 7 "const_int_operand" " i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (plus:VF_ZVE32 (vec_duplicate:VF_ZVE32 (vec_select: @@ -7425,8 +7583,10 @@ (match_operand 5 "vector_length_operand" " rK, rK") (match_operand 6 "const_int_operand" " i, i") (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (match_operand:VWF 3 "register_operand" " vr, vr") (match_operand: 4 "register_operand" " vr, vr") (match_operand: 2 "vector_merge_operand" " vu, 0")] UNSPEC_WREDUC_SUM)] ORDER))] @@ -7444,8 +7604,10 @@ (match_operand 5 "vector_length_operand" " rK, rK") (match_operand 6 "const_int_operand" " i, i") (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (match_operand:VWF_ZVE64 3 "register_operand" " vr, vr") (match_operand: 4 "register_operand" " vr, vr") (match_operand: 2 "vector_merge_operand" " vu, 0")] UNSPEC_WREDUC_SUM)] ORDER))] -- 2.36.3