From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from out30-97.freemail.mail.aliyun.com (out30-97.freemail.mail.aliyun.com [115.124.30.97]) by sourceware.org (Postfix) with ESMTPS id 1F4FD3858D1E for ; Wed, 17 May 2023 09:08:20 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 1F4FD3858D1E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.alibaba.com X-Alimail-AntiSpam:AC=PASS;BC=-1|-1;BR=01201311R401e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=ay29a033018046056;MF=jinma@linux.alibaba.com;NM=1;PH=DS;RN=5;SR=0;TI=SMTPD_---0Vis6sTN_1684314495; Received: from localhost.localdomain(mailfrom:jinma@linux.alibaba.com fp:SMTPD_---0Vis6sTN_1684314495) by smtp.aliyun-inc.com; Wed, 17 May 2023 17:08:17 +0800 From: Jin Ma To: gcc-patches@gcc.gnu.org Cc: jeffreyalaw@gmail.com, kito.cheng@gmail.com, jinma.contrib@gmail.com, Jin Ma Subject: [PATCH] RISC-V: Remove trailing spaces on lines. Date: Wed, 17 May 2023 17:08:03 +0800 Message-Id: <20230517090803.813-1-jinma@linux.alibaba.com> X-Mailer: git-send-email 2.38.1.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-20.5 required=5.0 tests=BAYES_00,ENV_AND_HDR_SPF_MATCH,GIT_PATCH_0,KAM_DMARC_STATUS,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY,USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Remove trailing spaces on lines. * config/riscv/riscv.cc (riscv_legitimize_move): Likewise. * config/riscv/riscv.h (enum reg_class): Likewise. * config/riscv/riscv.md: Likewise. --- gcc/common/config/riscv/riscv-common.cc | 2 +- gcc/config/riscv/riscv.cc | 6 +++--- gcc/config/riscv/riscv.h | 2 +- gcc/config/riscv/riscv.md | 4 ++-- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 3a285dfbff0..e46ddf78132 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -104,7 +104,7 @@ static const riscv_implied_info_t riscv_implied_info[] = {"zfh", "zfhmin"}, {"zfhmin", "f"}, - + {"zhinx", "zhinxmin"}, {"zhinxmin", "zfinx"}, diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index b52e613c629..1eb3e142905 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -2166,8 +2166,8 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src) } return true; } - /* Expand - (set (reg:QI target) (mem:QI (address))) + /* Expand + (set (reg:QI target) (mem:QI (address))) to (set (reg:DI temp) (zero_extend:DI (mem:QI (address)))) (set (reg:QI target) (subreg:QI (reg:DI temp) 0)) @@ -2182,7 +2182,7 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src) temp_reg = gen_reg_rtx (word_mode); zero_extend_p = (LOAD_EXTEND_OP (mode) == ZERO_EXTEND); - emit_insn (gen_extend_insn (temp_reg, src, word_mode, mode, + emit_insn (gen_extend_insn (temp_reg, src, word_mode, mode, zero_extend_p)); riscv_emit_move (dest, gen_lowpart (mode, temp_reg)); return true; diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index f74b70de562..70087d011f4 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -575,7 +575,7 @@ enum reg_class #define POLY_SMALL_OPERAND_P(POLY_VALUE) \ (POLY_VALUE.is_constant () ? \ SMALL_OPERAND (POLY_VALUE.to_constant ()) : false) - + /* True if VALUE can be loaded into a register using LUI. */ #define LUI_OPERAND(VALUE) \ diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index c5cf3af9868..f47ebb3a829 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -222,7 +222,7 @@ (define_attr "ext" "base,f,d,vector" (define_attr "ext_enabled" "no,yes" (cond [(eq_attr "ext" "base") (const_string "yes") - + (and (eq_attr "ext" "f") (match_test "TARGET_HARD_FLOAT")) (const_string "yes") @@ -258,7 +258,7 @@ (define_attr "enabled" "no,yes" ;; logical integer logical instructions ;; shift integer shift instructions ;; slt set less than instructions -;; imul integer multiply +;; imul integer multiply ;; idiv integer divide ;; move integer register move (addi rd, rs1, 0) ;; fmove floating point register move -- 2.17.1