From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pl1-x631.google.com (mail-pl1-x631.google.com [IPv6:2607:f8b0:4864:20::631]) by sourceware.org (Postfix) with ESMTPS id 7A82B3858D39 for ; Thu, 18 May 2023 20:57:23 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 7A82B3858D39 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-1ae4c5e12edso20058955ad.3 for ; Thu, 18 May 2023 13:57:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1684443442; x=1687035442; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=JeuwKewrwUQyFdTyEOHY5lDFHEzvByI7VmZujNmYsWE=; b=Wwzt9hS88+t5+fIT4hGEByi/ECGoeASUmJUCIvZi3MlyGa7UjTn/j/zKet7a0kKZY5 vOvKcPnJ48r1Qom57rWqdKZuFUGIH1bajRC7jbeDwDomjLwBopWdDgsb0yNPae/DjKgU YBNIilWbJOPmHfIOzRaiV9qEOx5A5I25QtWeR1YhEpqfmJl/DUhD7nlThbCvOLs6F9GQ 3eVPE7dqWdM/08h27WXQhcxWD7l+AZ53I2mT/KanoPAshuzvamOhVITQslo62J9yrhwK Ix2M3EmXKKVIaxTufGu/LxrIHpElHlVODE0g0xld+7qFsgVk7zztsgOkTgkgrDiB0LpO D+wQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684443442; x=1687035442; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=JeuwKewrwUQyFdTyEOHY5lDFHEzvByI7VmZujNmYsWE=; b=Cw9Dr3H/IBXGjv8KcHOWPtDXcZudVwJRtD5w1KoSZC07P1/SVUItoXO7OPHqi9qpxX elA/eIQt5a/86PofHZXn5hhjuz7+FP5DpdzNBRtxylGl8AAfRFtv8WdJOFck6TonznIc g4emi6DOcEuWA3Qhxdz6HuPFeZZY+tuWbr0LWNpv5omI6Fx0rrxz+WX3bJ00rqqMEtFK +4gkMxcDhQndyY/D9WsMFCwZwaQR+32hV8HsSKLQheuDzpE1D4h1jhonidDlGOWXpo9B wHf1NoHY8pJSXnkUMetyk4p5rXM3+l/A47zKaGH83m/SomOX/A45bROCUaQAH1nAD/2V KVWw== X-Gm-Message-State: AC+VfDw9sXsclFBMfkYPw+36BbHuiWqY08L7a9eZFiOcNohoMlSMkij6 LZf9rleBs/uhXifi41YmgwjB3pvmqKXSyAwtHu4= X-Google-Smtp-Source: ACHHUZ7WAuuN5ev47GP8SYZb3BHwUmmaSNv97Nb4etRQKsbtEqapUVGXIT2ghZx2GP7SUC7h19UsJw== X-Received: by 2002:a17:902:7289:b0:1ac:6084:1f4 with SMTP id d9-20020a170902728900b001ac608401f4mr423060pll.27.1684443442293; Thu, 18 May 2023 13:57:22 -0700 (PDT) Received: from vineet-framework.ba.rivosinc.com ([71.202.114.183]) by smtp.gmail.com with ESMTPSA id jj5-20020a170903048500b001ac82e8491csm1203644plb.282.2023.05.18.13.57.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 May 2023 13:57:21 -0700 (PDT) From: Vineet Gupta To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Jeff Law , Palmer Dabbelt , Christoph Mullner , gnu-toolchain@rivosinc.com, Vineet Gupta Subject: [PATCH] RISC-V: improve codegen for large constants with same 32-bit lo and hi parts [2] Date: Thu, 18 May 2023 13:57:16 -0700 Message-Id: <20230518205716.3258223-1-vineetg@rivosinc.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: [part #2 of PR/109279] SPEC2017 deepsjeng uses large constants which currently generates less than ideal code. This fix improves codegen for large constants which have same low and hi parts: e.g. long long f(void) { return 0x0101010101010101ull; } Before li a5,0x1010000 addi a5,a5,0x101 mv a0,a5 slli a5,a5,32 add a0,a5,a0 ret With patch li a5,0x1010000 addi a5,a5,0x101 slli a0,a5,32 add a0,a0,a5 ret This is testsuite clean. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_split_integer): if loval is equal to hival, ASHIFT the corresponding regs. Signed-off-by: Vineet Gupta --- gcc/config/riscv/riscv.cc | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 79122699b6f5..4e1bb2f14cf8 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -703,13 +703,18 @@ riscv_split_integer (HOST_WIDE_INT val, machine_mode mode) unsigned HOST_WIDE_INT hival = sext_hwi ((val - loval) >> 32, 32); rtx hi = gen_reg_rtx (mode), lo = gen_reg_rtx (mode); - riscv_move_integer (hi, hi, hival, mode); riscv_move_integer (lo, lo, loval, mode); - hi = gen_rtx_fmt_ee (ASHIFT, mode, hi, GEN_INT (32)); - hi = force_reg (mode, hi); + if (loval == hival) + hi = gen_rtx_ASHIFT (mode, lo, GEN_INT (32)); + else + { + riscv_move_integer (hi, hi, hival, mode); + hi = gen_rtx_ASHIFT (mode, hi, GEN_INT (32)); + } - return gen_rtx_fmt_ee (PLUS, mode, hi, lo); + hi = force_reg (mode, hi); + return gen_rtx_PLUS (mode, hi, lo); } /* Return true if X is a thread-local symbol. */ -- 2.34.1