From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by sourceware.org (Postfix) with ESMTPS id 1301D3858D32 for ; Mon, 29 May 2023 13:03:44 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 1301D3858D32 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1685365424; x=1716901424; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=3tCbostsr82ld3Yf4ubQUJNcdcEAoflje+1jh9y2t/Y=; b=VER7lPyap4Yt46Tsf4fy/LUFcbLzNkIDmvpPvQCE3SsjwCe8ogUrdR79 JIQkm9CRm2BfnBsHpi5CV4miDiUPacLskohMv55FaUBrsFpTfLkXqopEz /gdHyNlyLgUPaqcsELdyoo47UkiskM5U8Ta4oJhyVdZ0q4C5R5RDA/z0o +Z/xmD5efLv303b8+fvauczy7gFyyL1GH/RVp1DqwsGOHIPsq0R15RqI6 KHAZj9+eREaoYLg7EBleRsYIUy7AxTQUL/QugMA0I/K2KITcIf/JCjSt4 l0nfwt0lt/oWL1LTmOS2UqoJTnq+vRtchEt6CMGG/OKFAr8+xvywmQPuR A==; X-IronPort-AV: E=McAfee;i="6600,9927,10725"; a="339289143" X-IronPort-AV: E=Sophos;i="6.00,201,1681196400"; d="scan'208";a="339289143" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 May 2023 06:03:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10725"; a="775932550" X-IronPort-AV: E=Sophos;i="6.00,201,1681196400"; d="scan'208";a="775932550" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga004.fm.intel.com with ESMTP; 29 May 2023 06:03:38 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 2FD141005686; Mon, 29 May 2023 21:03:38 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@sifive.com, pan2.li@intel.com, yanzhang.wang@intel.com, rdapp.gcc@gmail.com Subject: [PATCH v1] RISC-V: Refactor comments and naming of riscv-v.cc. Date: Mon, 29 May 2023 21:03:36 +0800 Message-Id: <20230529130336.857998-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Pan Li This patch would like to remove unnecessary comments of some self explained parameters and try a better name to avoid misleading. Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv-v.cc (emit_vlmax_insn): Remove unnecessary comments and rename local variables. (emit_nonvlmax_insn): Diito. (emit_vlmax_merge_insn): Ditto. (emit_vlmax_cmp_insn): Ditto. (emit_vlmax_cmp_mu_insn): Ditto. (emit_scalar_move_insn): Ditto. Signed-off-by: Pan Li --- gcc/config/riscv/riscv-v.cc | 96 +++++++++++++++++++------------------ 1 file changed, 49 insertions(+), 47 deletions(-) diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 20b589bf51b..6ec24dba98d 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -349,16 +349,16 @@ autovec_use_vlmax_p (void) void emit_vlmax_insn (unsigned icode, int op_num, rtx *ops, rtx vl) { - machine_mode data_mode = GET_MODE (ops[0]); - machine_mode mask_mode = get_mask_mode (data_mode).require (); - insn_expander e (/*OP_NUM*/ op_num, - /*HAS_DEST_P*/ true, - /*FULLY_UNMASKED_P*/ true, - /*USE_REAL_MERGE_P*/ false, - /*HAS_AVL_P*/ true, - /*VLMAX_P*/ true, - /*DEST_MODE*/ data_mode, - /*MASK_MODE*/ mask_mode); + machine_mode dest_mode = GET_MODE (ops[0]); + machine_mode mask_mode = get_mask_mode (dest_mode).require (); + insn_expander e (op_num, + /* HAS_DEST_P */ true, + /* FULLY_UNMASKED_P */ true, + /* USE_REAL_MERGE_P */ false, + /* HAS_AVL_P */ true, + /* VLMAX_P */ true, + dest_mode, + mask_mode); e.set_policy (TAIL_ANY); e.set_policy (MASK_ANY); @@ -373,16 +373,16 @@ emit_vlmax_insn (unsigned icode, int op_num, rtx *ops, rtx vl) void emit_nonvlmax_insn (unsigned icode, int op_num, rtx *ops, rtx avl) { - machine_mode data_mode = GET_MODE (ops[0]); - machine_mode mask_mode = get_mask_mode (data_mode).require (); - insn_expander e (/*OP_NUM*/ op_num, - /*HAS_DEST_P*/ true, - /*FULLY_UNMASKED_P*/ true, - /*USE_REAL_MERGE_P*/ false, - /*HAS_AVL_P*/ true, - /*VLMAX_P*/ false, - /*DEST_MODE*/ data_mode, - /*MASK_MODE*/ mask_mode); + machine_mode dest_mode = GET_MODE (ops[0]); + machine_mode mask_mode = get_mask_mode (dest_mode).require (); + insn_expander e (op_num, + /* HAS_DEST_P */ true, + /* FULLY_UNMASKED_P */ true, + /* USE_REAL_MERGE_P */ false, + /* HAS_AVL_P */ true, + /* VLMAX_P */ false, + dest_mode, + mask_mode); e.set_policy (TAIL_ANY); e.set_policy (MASK_ANY); @@ -396,14 +396,14 @@ emit_vlmax_merge_insn (unsigned icode, int op_num, rtx *ops) { machine_mode dest_mode = GET_MODE (ops[0]); machine_mode mask_mode = get_mask_mode (dest_mode).require (); - insn_expander e (/*OP_NUM*/ op_num, - /*HAS_DEST_P*/ true, - /*FULLY_UNMASKED_P*/ false, - /*USE_REAL_MERGE_P*/ false, - /*HAS_AVL_P*/ true, - /*VLMAX_P*/ true, - /*DEST_MODE*/ dest_mode, - /*MASK_MODE*/ mask_mode); + insn_expander e (op_num, + /* HAS_DEST_P */ true, + /* FULLY_UNMASKED_P */ false, + /* USE_REAL_MERGE_P */ false, + /* HAS_AVL_P */ true, + /* VLMAX_P */ true, + dest_mode, + mask_mode); e.set_policy (TAIL_ANY); e.emit_insn ((enum insn_code) icode, ops); @@ -414,14 +414,14 @@ void emit_vlmax_cmp_insn (unsigned icode, rtx *ops) { machine_mode mode = GET_MODE (ops[0]); - insn_expander e (/*OP_NUM*/ RVV_CMP_OP, - /*HAS_DEST_P*/ true, - /*FULLY_UNMASKED_P*/ true, - /*USE_REAL_MERGE_P*/ false, - /*HAS_AVL_P*/ true, - /*VLMAX_P*/ true, - /*DEST_MODE*/ mode, - /*MASK_MODE*/ mode); + insn_expander e (RVV_CMP_OP, + /* HAS_DEST_P */ true, + /* FULLY_UNMASKED_P */ true, + /* USE_REAL_MERGE_P */ false, + /* HAS_AVL_P */ true, + /* VLMAX_P */ true, + mode, + mode); e.set_policy (MASK_ANY); e.emit_insn ((enum insn_code) icode, ops); @@ -432,14 +432,14 @@ void emit_vlmax_cmp_mu_insn (unsigned icode, rtx *ops) { machine_mode mode = GET_MODE (ops[0]); - insn_expander e (/*OP_NUM*/ RVV_CMP_MU_OP, - /*HAS_DEST_P*/ true, - /*FULLY_UNMASKED_P*/ false, - /*USE_REAL_MERGE_P*/ true, - /*HAS_AVL_P*/ true, - /*VLMAX_P*/ true, - /*DEST_MODE*/ mode, - /*MASK_MODE*/ mode); + insn_expander e (RVV_CMP_MU_OP, + /* HAS_DEST_P */ true, + /* FULLY_UNMASKED_P */ false, + /* USE_REAL_MERGE_P */ true, + /* HAS_AVL_P */ true, + /* VLMAX_P */ true, + mode, + mode); e.set_policy (MASK_UNDISTURBED); e.emit_insn ((enum insn_code) icode, ops); @@ -1450,15 +1450,17 @@ expand_vector_init_insert_elems (rtx target, const rvv_builder &builder, static void emit_scalar_move_insn (unsigned icode, rtx *ops) { - machine_mode data_mode = GET_MODE (ops[0]); - machine_mode mask_mode = get_mask_mode (data_mode).require (); + machine_mode dest_mode = GET_MODE (ops[0]); + machine_mode mask_mode = get_mask_mode (dest_mode).require (); insn_expander e (riscv_vector::RVV_SCALAR_MOV_OP, /* HAS_DEST_P */ true, /* FULLY_UNMASKED_P */ false, /* USE_REAL_MERGE_P */ true, /* HAS_AVL_P */ true, /* VLMAX_P */ false, - data_mode, mask_mode); + dest_mode, + mask_mode); + e.set_policy (TAIL_ANY); e.set_policy (MASK_ANY); e.set_vl (CONST1_RTX (Pmode)); -- 2.34.1