From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by sourceware.org (Postfix) with ESMTPS id 1350E3858416 for ; Tue, 6 Jun 2023 12:36:51 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 1350E3858416 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1686055012; x=1717591012; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=Ny1Z91NUShpOHRipNKyTLermacgujHgVlojFjzalfaw=; b=Ho5ATgY8YTVKchOHEShuHlbAqBg5TuC1W0P5W5EUWmaOEbE0ejAssfeu mQ9LvKuuqVp5vgRMnp/sD+TdnOh7z7eFwwiQ4gPX5n4INxS/8Lbpeq2If U2KQeA/xziK6F69A485i7MhcjuiExwp+h4dJWn+ClviN81EJ1MS/EGJW3 fcJHj53r6ICmbAIpLdK+n/oC6bt91c8WMCog+46hdLFKSNR+PzYgmJ8H2 GnhXL0eUcW5Z9/Cr2jnzyHRbokeczUzN2Tfza6GdCh/nNOVJAdGrikiVG uRJHbQHQfHBUVQho/sJmMQKqWXW+n10EMAv0QJpXpv0NF6GDhsLjQmkqo A==; X-IronPort-AV: E=McAfee;i="6600,9927,10732"; a="346255005" X-IronPort-AV: E=Sophos;i="6.00,221,1681196400"; d="scan'208";a="346255005" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2023 05:36:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10732"; a="742134482" X-IronPort-AV: E=Sophos;i="6.00,221,1681196400"; d="scan'208";a="742134482" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga001.jf.intel.com with ESMTP; 06 Jun 2023 05:36:48 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 5033F10054DE; Tue, 6 Jun 2023 20:36:47 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@sifive.com, pan2.li@intel.com, yanzhang.wang@intel.com Subject: [PATCH v1] RISC-V: Refactor ZVFHMIN to separated iterator and pattern Date: Tue, 6 Jun 2023 20:36:46 +0800 Message-Id: <20230606123646.1553843-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_ASCII_DIVIDERS,KAM_SHORT,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Pan Li This patch would like to refactor the ZVFHMIN implementation by separated iterator and pattern. Thus, we can tell the sub extension between the ZVFHMIN and ZVFH. Please note the ZVFH will cover the ZVFHMIN instructions. This patch add one test for this. Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/vector-iterators.md: Move ZVFHMIN related items to separated iterators. * config/riscv/vector.md (@pred_extend): New pattern for the ZVFHMIN instruction. (@pred_trunc): Likewise. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: New test. --- gcc/config/riscv/vector-iterators.md | 28 ++++++++----- gcc/config/riscv/vector.md | 40 +++++++++++++++++++ .../riscv/rvv/base/zvfh-over-zvfhmin.c | 25 ++++++++++++ 3 files changed, 83 insertions(+), 10 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index f4946d84449..986195489f2 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -497,13 +497,6 @@ (define_mode_iterator VWEXTI [ ]) (define_mode_iterator VWEXTF [ - (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128") - (VNx2SF "TARGET_VECTOR_ELEN_FP_32") - (VNx4SF "TARGET_VECTOR_ELEN_FP_32") - (VNx8SF "TARGET_VECTOR_ELEN_FP_32") - (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") - (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128") - (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128") (VNx2DF "TARGET_VECTOR_ELEN_FP_64") (VNx4DF "TARGET_VECTOR_ELEN_FP_64") @@ -511,6 +504,15 @@ (define_mode_iterator VWEXTF [ (VNx16DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128") ]) +(define_mode_iterator V_ZVFHMIN_SF [ + (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && TARGET_MIN_VLEN < 128") + (VNx2SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)") + (VNx4SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)") + (VNx8SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)") + (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && TARGET_MIN_VLEN > 32") + (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && TARGET_MIN_VLEN >= 128") +]) + (define_mode_iterator VWCONVERTI [ (VNx1SI "TARGET_MIN_VLEN < 128 && TARGET_VECTOR_ELEN_FP_16") (VNx2SI "TARGET_VECTOR_ELEN_FP_16") @@ -1175,12 +1177,19 @@ (define_mode_attr V_DOUBLE_TRUNC [ (VNx16SI "VNx16HI") (VNx32SI "VNx32HI") (VNx1DI "VNx1SI") (VNx2DI "VNx2SI") (VNx4DI "VNx4SI") (VNx8DI "VNx8SI") (VNx16DI "VNx16SI") - - (VNx1SF "VNx1HF") (VNx2SF "VNx2HF") (VNx4SF "VNx4HF") (VNx8SF "VNx8HF") (VNx16SF "VNx16HF") (VNx32SF "VNx32HF") (VNx1DF "VNx1SF") (VNx2DF "VNx2SF") (VNx4DF "VNx4SF") (VNx8DF "VNx8SF") (VNx16DF "VNx16SF") ]) +(define_mode_attr V_ZVFHMIN [ + (VNx1SF "VNx1HF") + (VNx2SF "VNx2HF") + (VNx4SF "VNx4HF") + (VNx8SF "VNx8HF") + (VNx16SF "VNx16HF") + (VNx32SF "VNx32HF") +]) + (define_mode_attr V_QUAD_TRUNC [ (VNx1SI "VNx1QI") (VNx2SI "VNx2QI") (VNx4SI "VNx4QI") (VNx8SI "VNx8QI") (VNx16SI "VNx16QI") (VNx32SI "VNx32QI") @@ -1201,7 +1210,6 @@ (define_mode_attr v_double_trunc [ (VNx16SI "vnx16hi") (VNx32SI "vnx32hi") (VNx1DI "vnx1si") (VNx2DI "vnx2si") (VNx4DI "vnx4si") (VNx8DI "vnx8si") (VNx16DI "vnx16si") - (VNx1SF "vnx1hf") (VNx2SF "vnx2hf") (VNx4SF "vnx4hf") (VNx8SF "vnx8hf") (VNx16SF "vnx16hf") (VNx32SF "vnx32hf") (VNx1DF "vnx1sf") (VNx2DF "vnx2sf") (VNx4DF "vnx4sf") (VNx8DF "vnx8sf") (VNx16DF "vnx16sf") ]) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 1d1847bd85a..b498669b874 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -7124,6 +7124,25 @@ (define_insn "@pred_extend" [(set_attr "type" "vfwcvtftof") (set_attr "mode" "")]) +(define_insn "@pred_extend" + [(set (match_operand:V_ZVFHMIN_SF 0 "register_operand" "=&vr, &vr") + (if_then_else:V_ZVFHMIN_SF + (unspec: + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 4 "vector_length_operand" " rK, rK") + (match_operand 5 "const_int_operand" " i, i") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (float_extend:V_ZVFHMIN_SF + (match_operand: 3 "register_operand" " vr, vr")) + (match_operand:V_ZVFHMIN_SF 2 "vector_merge_operand" " vu, 0")))] + "TARGET_VECTOR" + "vfwcvt.f.f.v\t%0,%3%p1" + [(set_attr "type" "vfwcvtftof") + (set_attr "mode" "")]) + ;; ------------------------------------------------------------------------------- ;; ---- Predicated floating-point narrow conversions ;; ------------------------------------------------------------------------------- @@ -7213,6 +7232,27 @@ (define_insn "@pred_trunc" [(set_attr "type" "vfncvtftof") (set_attr "mode" "")]) +(define_insn "@pred_trunc" + [(set (match_operand: 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr") + (if_then_else: + (unspec: + [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1") + (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK") + (match_operand 5 "const_int_operand" " i, i, i, i, i, i") + (match_operand 6 "const_int_operand" " i, i, i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i, i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) + (float_truncate: + (match_operand:V_ZVFHMIN_SF 3 "register_operand" " 0, 0, 0, 0, vr, vr")) + (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))] + "TARGET_VECTOR" + "vfncvt.f.f.w\t%0,%3%p1" + [(set_attr "type" "vfncvtftof") + (set_attr "mode" "")]) + (define_insn "@pred_rod_trunc" [(set (match_operand: 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr") (if_then_else: diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c new file mode 100644 index 00000000000..32d6657775c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */ + +#include "riscv_vector.h" + +vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) { + return __riscv_vfncvt_f_f_w_f16mf4(src, vl); +} + +vfloat16m4_t test_vfncvt_f_f_w_f16m4(vfloat32m8_t src, size_t vl) { + return __riscv_vfncvt_f_f_w_f16m4(src, vl); +} + +vfloat32mf2_t test_vfwcvt_f_f_v_f32mf2(vfloat16mf4_t src, size_t vl) { + return __riscv_vfwcvt_f_f_v_f32mf2(src, vl); +} + +vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) { + return __riscv_vfwcvt_f_f_v_f32m8(src, vl); +} + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */ +/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */ -- 2.34.1