From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from zg8tmja2lje4os4yms4ymjma.icoremail.net (zg8tmja2lje4os4yms4ymjma.icoremail.net [206.189.21.223]) by sourceware.org (Postfix) with ESMTP id 0D73E3857727 for ; Wed, 7 Jun 2023 05:52:40 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 0D73E3857727 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=eswincomputing.com Received: from localhost.localdomain (unknown [10.12.130.31]) by app1 (Coremail) with SMTP id EwgMCgBnBcUeG4BkrggjAA--.24178S8; Wed, 07 Jun 2023 13:52:37 +0800 (CST) From: Fei Gao To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, jeffreyalaw@gmail.com, sinan.lin@linux.alibaba.com, jiawei@iscas.ac.cn, Die Li Subject: [PATCH 4/4] [RISC-V] support cm.mva01s cm.mvsa01 in zcmp Date: Wed, 7 Jun 2023 05:52:15 +0000 Message-Id: <20230607055215.29332-5-gaofei@eswincomputing.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230607055215.29332-1-gaofei@eswincomputing.com> References: <20230607055215.29332-1-gaofei@eswincomputing.com> X-CM-TRANSID:EwgMCgBnBcUeG4BkrggjAA--.24178S8 X-Coremail-Antispam: 1UD129KBjvJXoW3JFW8Zw4kJrykAr4xAry3CFg_yoW7WrWDpr WUKw15CrW8Zrs3K34fKFWxXw4Ykrs3KFWYy39xC3sFkw4UJryDtF1vkFyaqFZrXF4ftr43 Ca1Ik3yY9w1Yk3DanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBa14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_tr0E3s1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr1j6r xdM28EF7xvwVC2z280aVAFwI0_GcCE3s1l84ACjcxK6I8E87Iv6xkF7I0E14v26rxl6s0D M2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjx v20xvE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1l F7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7MxkIecxEwVCm-wCF04k20x vY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I 3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_JF0_Jw1lIxkGc2Ij64vIr41lIx AIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1lIxAI cVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2js IEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x0JUQSdkUUUUU= X-CM-SenderInfo: xjdrwv3l6h245lqf0zpsxwx03jof0z/ X-Spam-Status: No, score=-10.6 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_SHORT,LIKELY_SPAM_BODY,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Die Li Signed-off-by: Die Li Co-Authored-By: Fei Gao gcc/ChangeLog: * config/riscv/peephole.md: New pattern. * config/riscv/predicates.md (a0a1_reg_operand): New predicate. (zcmp_mv_sreg_operand): New predicate. * config/riscv/riscv.md: New predicate. * config/riscv/zc.md (*mva01s): New pattern. (*mvsa01): New pattern. gcc/testsuite/ChangeLog: * gcc.target/riscv/cm_mv_rv32.c: New test. --- gcc/config/riscv/peephole.md | 28 +++++++++++++++++++++ gcc/config/riscv/predicates.md | 11 ++++++++ gcc/config/riscv/riscv.md | 1 + gcc/config/riscv/zc.md | 22 ++++++++++++++++ gcc/testsuite/gcc.target/riscv/cm_mv_rv32.c | 21 ++++++++++++++++ 5 files changed, 83 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/cm_mv_rv32.c diff --git a/gcc/config/riscv/peephole.md b/gcc/config/riscv/peephole.md index 67e7046d7e6..e8cb1ba4838 100644 --- a/gcc/config/riscv/peephole.md +++ b/gcc/config/riscv/peephole.md @@ -94,3 +94,31 @@ { th_mempair_order_operands (operands, true, SImode); }) + +;; ZCMP +(define_peephole2 + [(set (match_operand:X 0 "a0a1_reg_operand") + (match_operand:X 1 "zcmp_mv_sreg_operand")) + (set (match_operand:X 2 "a0a1_reg_operand") + (match_operand:X 3 "zcmp_mv_sreg_operand"))] + "TARGET_ZCMP + && (REGNO (operands[2]) != REGNO (operands[0]))" + [(parallel [(set (match_dup 0) + (match_dup 1)) + (set (match_dup 2) + (match_dup 3))])] +) + +(define_peephole2 + [(set (match_operand:X 0 "zcmp_mv_sreg_operand") + (match_operand:X 1 "a0a1_reg_operand")) + (set (match_operand:X 2 "zcmp_mv_sreg_operand") + (match_operand:X 3 "a0a1_reg_operand"))] + "TARGET_ZCMP + && (REGNO (operands[0]) != REGNO (operands[2])) + && (REGNO (operands[1]) != REGNO (operands[3]))" + [(parallel [(set (match_dup 0) + (match_dup 1)) + (set (match_dup 2) + (match_dup 3))])] +) diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index a1b9367b997..6d5e8630cb5 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -207,6 +207,17 @@ (and (match_code "const_int") (match_test "riscv_zcmp_valid_stack_adj_bytes_p (INTVAL (op), 13)"))) +;; ZCMP predicates +(define_predicate "a0a1_reg_operand" + (and (match_operand 0 "register_operand") + (match_test "IN_RANGE (REGNO (op), A0_REGNUM, A1_REGNUM)"))) + +(define_predicate "zcmp_mv_sreg_operand" + (and (match_operand 0 "register_operand") + (match_test "TARGET_RVE ? IN_RANGE (REGNO (op), S0_REGNUM, S1_REGNUM) + : IN_RANGE (REGNO (op), S0_REGNUM, S1_REGNUM) + || IN_RANGE (REGNO (op), S2_REGNUM, S7_REGNUM)"))) + ;; Only use branch-on-bit sequences when the mask is not an ANDI immediate. (define_predicate "branch_on_bit_operand" (and (match_code "const_int") diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 02802d2685d..25bc3e6ab4c 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -121,6 +121,7 @@ (S0_REGNUM 8) (S1_REGNUM 9) (A0_REGNUM 10) + (A1_REGNUM 11) (S2_REGNUM 18) (S3_REGNUM 19) (S4_REGNUM 20) diff --git a/gcc/config/riscv/zc.md b/gcc/config/riscv/zc.md index 217e115035b..bb4975cd333 100644 --- a/gcc/config/riscv/zc.md +++ b/gcc/config/riscv/zc.md @@ -1433,3 +1433,25 @@ "TARGET_ZCMP" "cm.push {ra, s0-s11}, %0" ) + +;; ZCMP mv +(define_insn "*mva01s" + [(set (match_operand:X 0 "a0a1_reg_operand" "=r") + (match_operand:X 1 "zcmp_mv_sreg_operand" "r")) + (set (match_operand:X 2 "a0a1_reg_operand" "=r") + (match_operand:X 3 "zcmp_mv_sreg_operand" "r"))] + "TARGET_ZCMP + && (REGNO (operands[2]) != REGNO (operands[0]))" + { return (REGNO (operands[0]) == A0_REGNUM)?"cm.mva01s\t%1,%3":"cm.mva01s\t%3,%1"; } + [(set_attr "mode" "")]) + +(define_insn "*mvsa01" + [(set (match_operand:X 0 "zcmp_mv_sreg_operand" "=r") + (match_operand:X 1 "a0a1_reg_operand" "r")) + (set (match_operand:X 2 "zcmp_mv_sreg_operand" "=r") + (match_operand:X 3 "a0a1_reg_operand" "r"))] + "TARGET_ZCMP + && (REGNO (operands[0]) != REGNO (operands[2])) + && (REGNO (operands[1]) != REGNO (operands[3]))" + { return (REGNO (operands[1]) == A0_REGNUM)?"cm.mvsa01\t%0,%2":"cm.mvsa01\t%2,%0"; } + [(set_attr "mode" "")]) diff --git a/gcc/testsuite/gcc.target/riscv/cm_mv_rv32.c b/gcc/testsuite/gcc.target/riscv/cm_mv_rv32.c new file mode 100644 index 00000000000..49c94c01603 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cm_mv_rv32.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options " -Os -march=rv32i_zca_zcmp -mabi=ilp32 " } */ +/* { dg-skip-if "" { *-*-* } {"-O0" "-O1" "-O2" "-Og" "-O3" "-Oz" "-flto"} } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +int func (int a, int b); + +/* +**sum: +** ... +** cm.mvsa01 s1,s2 +** call func +** mv s0,a0 +** cm.mva01s s1,s2 +** call func +** ... +*/ +int sum (int a, int b) +{ + return func (a, b) + func (a, b); +} -- 2.17.1