From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by sourceware.org (Postfix) with ESMTPS id 53BF4385842C for ; Wed, 7 Jun 2023 08:06:15 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 53BF4385842C Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1686125175; x=1717661175; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pa3NAC8Fc7SQWeKRbZCKpXkko4U95Z8H/2lFnhul8SI=; b=e4axdFH4FF+kj+nwcTqwB3xZHpNkfvSnd3c8rxzXp44mHut5tebkhH20 oCPN54B57QEMxUwJ9q6rbXir9zbsDJaaUHO32caxMgIJq8zPu5Z8G3yUb SxsVh3ykDzR99SEuw7PYObggmnnIU3Nb5kDEExWxS4S9rQ8VhOi8OC9bY pJGPVaCyHX4x4XmL/rwA5aUqrRfYDY5BlckcKJkF4EHd7Z5ehsASEtN7n Q5HtQhZBOP4uB46/wlJKIET87RqE5s7H4lhuZJvUzZUiK9bTnim2RKURB AxdEeHSV+k45OGot1nStEQJfuolCpW7MFs/CMTHbLIkXPMNh+UMQg4qD0 g==; X-IronPort-AV: E=McAfee;i="6600,9927,10733"; a="443286533" X-IronPort-AV: E=Sophos;i="6.00,223,1681196400"; d="scan'208";a="443286533" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jun 2023 01:06:14 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10733"; a="779297793" X-IronPort-AV: E=Sophos;i="6.00,223,1681196400"; d="scan'208";a="779297793" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga004.fm.intel.com with ESMTP; 07 Jun 2023 01:06:09 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id E2D4F1005129; Wed, 7 Jun 2023 16:06:08 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, rdapp.gcc@gmail.com, jeffreyalaw@gmail.com, pan2.li@intel.com, yanzhang.wang@intel.com Subject: [PATCH v5] RISC-V: Refactor requirement of ZVFH and ZVFHMIN. Date: Wed, 7 Jun 2023 16:06:06 +0800 Message-Id: <20230607080606.2104805-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230606123646.1553843-1-pan2.li@intel.com> References: <20230606123646.1553843-1-pan2.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Pan Li This patch would like to refactor the requirement of both the ZVFH and ZVFHMIN. The related define_insn and iterator will take the requirement based on the ZVFHMIN and ZVFH. Please note the ZVFH will cover the ZVFHMIN instructions. This patch add one test for this. Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/vector-iterators.md: Add requirement to VF, VWEXTF and VWCONVERTI, add V_CONVERT_F and VCONVERTF. * config/riscv/vector.md: Adjust FP convert to V_CONVERT_F and VCONVERTF, and fix V_WHOLE and V_FRACT. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: New test. --- gcc/config/riscv/vector-iterators.md | 79 +++++++++++++------ gcc/config/riscv/vector.md | 46 +++++------ .../riscv/rvv/base/zvfh-over-zvfhmin.c | 25 ++++++ 3 files changed, 104 insertions(+), 46 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index f4946d84449..e6c2ecf7c86 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -296,13 +296,13 @@ (define_mode_iterator VWI_ZVE32 [ ]) (define_mode_iterator VF [ - (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128") - (VNx2HF "TARGET_VECTOR_ELEN_FP_16") - (VNx4HF "TARGET_VECTOR_ELEN_FP_16") - (VNx8HF "TARGET_VECTOR_ELEN_FP_16") - (VNx16HF "TARGET_VECTOR_ELEN_FP_16") - (VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") - (VNx64HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128") + (VNx1HF "TARGET_ZVFH && TARGET_MIN_VLEN < 128") + (VNx2HF "TARGET_ZVFH") + (VNx4HF "TARGET_ZVFH") + (VNx8HF "TARGET_ZVFH") + (VNx16HF "TARGET_ZVFH") + (VNx32HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32") + (VNx64HF "TARGET_ZVFH && TARGET_MIN_VLEN >= 128") (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128") (VNx2SF "TARGET_VECTOR_ELEN_FP_32") @@ -453,9 +453,8 @@ (define_mode_iterator V_WHOLE [ (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64") (VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128") - (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128") - (VNx2HF "TARGET_VECTOR_ELEN_FP_16") - (VNx4HF "TARGET_VECTOR_ELEN_FP_16") + (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 32") + (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 64") (VNx8HF "TARGET_VECTOR_ELEN_FP_16") (VNx16HF "TARGET_VECTOR_ELEN_FP_16") (VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") @@ -477,7 +476,11 @@ (define_mode_iterator V_WHOLE [ (define_mode_iterator V_FRACT [ (VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI (VNx4QI "TARGET_MIN_VLEN > 32") (VNx8QI "TARGET_MIN_VLEN >= 128") (VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN > 32") (VNx4HI "TARGET_MIN_VLEN >= 128") - (VNx1HF "TARGET_MIN_VLEN < 128") (VNx2HF "TARGET_MIN_VLEN > 32") (VNx4HF "TARGET_MIN_VLEN >= 128") + + (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128") + (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") + (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128") + (VNx1SI "TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128") (VNx2SI "TARGET_MIN_VLEN >= 128") (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128") (VNx2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128") @@ -497,12 +500,12 @@ (define_mode_iterator VWEXTI [ ]) (define_mode_iterator VWEXTF [ - (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128") - (VNx2SF "TARGET_VECTOR_ELEN_FP_32") - (VNx4SF "TARGET_VECTOR_ELEN_FP_32") - (VNx8SF "TARGET_VECTOR_ELEN_FP_32") - (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") - (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128") + (VNx1SF "TARGET_ZVFH && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128") + (VNx2SF "TARGET_ZVFH && TARGET_VECTOR_ELEN_FP_32") + (VNx4SF "TARGET_ZVFH && TARGET_VECTOR_ELEN_FP_32") + (VNx8SF "TARGET_ZVFH && TARGET_VECTOR_ELEN_FP_32") + (VNx16SF "TARGET_ZVFH && TARGET_MIN_VLEN > 32") + (VNx32SF "TARGET_ZVFH && TARGET_MIN_VLEN >= 128") (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128") (VNx2DF "TARGET_VECTOR_ELEN_FP_64") @@ -512,12 +515,12 @@ (define_mode_iterator VWEXTF [ ]) (define_mode_iterator VWCONVERTI [ - (VNx1SI "TARGET_MIN_VLEN < 128 && TARGET_VECTOR_ELEN_FP_16") - (VNx2SI "TARGET_VECTOR_ELEN_FP_16") - (VNx4SI "TARGET_VECTOR_ELEN_FP_16") - (VNx8SI "TARGET_VECTOR_ELEN_FP_16") - (VNx16SI "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_FP_16") - (VNx32SI "TARGET_MIN_VLEN >= 128 && TARGET_VECTOR_ELEN_FP_16") + (VNx1SI "TARGET_ZVFH && TARGET_MIN_VLEN < 128") + (VNx2SI "TARGET_ZVFH") + (VNx4SI "TARGET_ZVFH") + (VNx8SI "TARGET_ZVFH") + (VNx16SI "TARGET_ZVFH && TARGET_MIN_VLEN > 32") + (VNx32SI "TARGET_ZVFH && TARGET_MIN_VLEN >= 128") (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32") @@ -526,6 +529,21 @@ (define_mode_iterator VWCONVERTI [ (VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128") ]) +(define_mode_iterator VCONVERTF [ + (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128") + (VNx2SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32") + (VNx4SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32") + (VNx8SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32") + (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") + (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128") + + (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128") + (VNx2DF "TARGET_VECTOR_ELEN_FP_64") + (VNx4DF "TARGET_VECTOR_ELEN_FP_64") + (VNx8DF "TARGET_VECTOR_ELEN_FP_64") + (VNx16DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128") +]) + (define_mode_iterator VQEXTI [ (VNx1SI "TARGET_MIN_VLEN < 128") VNx2SI VNx4SI VNx8SI (VNx16SI "TARGET_MIN_VLEN > 32") (VNx32SI "TARGET_MIN_VLEN >= 128") (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64") @@ -1181,6 +1199,21 @@ (define_mode_attr V_DOUBLE_TRUNC [ (VNx16DF "VNx16SF") ]) +(define_mode_attr V_CONVERT_F [ + (VNx1SF "VNx1HF") + (VNx2SF "VNx2HF") + (VNx4SF "VNx4HF") + (VNx8SF "VNx8HF") + (VNx16SF "VNx16HF") + (VNx32SF "VNx32HF") + + (VNx1DF "VNx1SF") + (VNx2DF "VNx2SF") + (VNx4DF "VNx4SF") + (VNx8DF "VNx8SF") + (VNx16DF "VNx16SF") +]) + (define_mode_attr V_QUAD_TRUNC [ (VNx1SI "VNx1QI") (VNx2SI "VNx2QI") (VNx4SI "VNx4QI") (VNx8SI "VNx8QI") (VNx16SI "VNx16QI") (VNx32SI "VNx32QI") diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 1d1847bd85a..97162b07642 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -7106,23 +7106,23 @@ (define_insn "@pred_widen_" (set_attr "mode" "")]) (define_insn "@pred_extend" - [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr") - (if_then_else:VWEXTF + [(set (match_operand:VCONVERTF 0 "register_operand" "=&vr, &vr") + (if_then_else:VCONVERTF (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") - (match_operand 4 "vector_length_operand" " rK, rK") - (match_operand 5 "const_int_operand" " i, i") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 4 "vector_length_operand" " rK, rK") + (match_operand 5 "const_int_operand" " i, i") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (float_extend:VWEXTF - (match_operand: 3 "register_operand" " vr, vr")) - (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))] + (float_extend:VCONVERTF + (match_operand: 3 "register_operand" " vr, vr")) + (match_operand:VCONVERTF 2 "vector_merge_operand" " vu, 0")))] "TARGET_VECTOR" "vfwcvt.f.f.v\t%0,%3%p1" [(set_attr "type" "vfwcvtftof") - (set_attr "mode" "")]) + (set_attr "mode" "")]) ;; ------------------------------------------------------------------------------- ;; ---- Predicated floating-point narrow conversions @@ -7193,25 +7193,25 @@ (define_insn "@pred_narrow_" (set_attr "mode" "")]) (define_insn "@pred_trunc" - [(set (match_operand: 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr") - (if_then_else: + [(set (match_operand: 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr") + (if_then_else: (unspec: - [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1") - (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK") - (match_operand 5 "const_int_operand" " i, i, i, i, i, i") - (match_operand 6 "const_int_operand" " i, i, i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i, i, i") + [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1") + (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK") + (match_operand 5 "const_int_operand" " i, i, i, i, i, i") + (match_operand 6 "const_int_operand" " i, i, i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM) (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) - (float_truncate: - (match_operand:VWEXTF 3 "register_operand" " 0, 0, 0, 0, vr, vr")) - (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))] + (float_truncate: + (match_operand:VCONVERTF 3 "register_operand" " 0, 0, 0, 0, vr, vr")) + (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))] "TARGET_VECTOR" "vfncvt.f.f.w\t%0,%3%p1" [(set_attr "type" "vfncvtftof") - (set_attr "mode" "")]) + (set_attr "mode" "")]) (define_insn "@pred_rod_trunc" [(set (match_operand: 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr") diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c new file mode 100644 index 00000000000..32d6657775c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */ + +#include "riscv_vector.h" + +vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) { + return __riscv_vfncvt_f_f_w_f16mf4(src, vl); +} + +vfloat16m4_t test_vfncvt_f_f_w_f16m4(vfloat32m8_t src, size_t vl) { + return __riscv_vfncvt_f_f_w_f16m4(src, vl); +} + +vfloat32mf2_t test_vfwcvt_f_f_v_f32mf2(vfloat16mf4_t src, size_t vl) { + return __riscv_vfwcvt_f_f_v_f32mf2(src, vl); +} + +vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) { + return __riscv_vfwcvt_f_f_v_f32m8(src, vl); +} + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */ +/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */ -- 2.34.1