From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by sourceware.org (Postfix) with ESMTPS id 21E553858D35 for ; Fri, 9 Jun 2023 23:59:09 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 21E553858D35 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1686355149; x=1717891149; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=qLouGZz4uIzoTn8X1KYfuKcQc2aBPJW27nffQFyBYYk=; b=Mq9hQlOiSCxLPQroirD5iK87PmDjhOwmZHg9roA9qowMKNNoCwIeufNj BImGtqBnNsGctoGThJ30Gdtz0Ba5XQkJJW4z5C39ja5IOhyRdyrx8a4Eu Ok2dyhzCya6RG9xDGIJxnAa/I1brmlt80tBvjo5YxXn/+mJ9eM9Q7UBfJ OF7nYmnGTgbxIRqPlhocbyIpzDfIvAQSSHeNs9y+8TIu8FX6/v5UjYdet t23K4Xok7VEgvuQPsUyOUquk1o+PgGk+1il8GgZlJBKfurhu9LePp5Vny /DjDzUAKO1uqJjUU7Doa60J9LnsuqrQkfe4R/G899mGEwmu79y6mjKVQp A==; X-IronPort-AV: E=McAfee;i="6600,9927,10736"; a="342385927" X-IronPort-AV: E=Sophos;i="6.00,230,1681196400"; d="scan'208";a="342385927" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jun 2023 16:59:08 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10736"; a="704719476" X-IronPort-AV: E=Sophos;i="6.00,230,1681196400"; d="scan'208";a="704719476" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga007.jf.intel.com with ESMTP; 09 Jun 2023 16:59:05 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 5B15B1005180; Sat, 10 Jun 2023 07:59:04 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, rdapp.gcc@gmail.com, jeffreyalaw@gmail.com, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Add test cases for RVV FP16 vreinterpret Date: Sat, 10 Jun 2023 07:59:02 +0800 Message-Id: <20230609235902.1270855-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Pan Li This patch would like to add more tests for RVV FP16 vreinterpret, aka vfloat16*_t <==> v{u}int16*_t. There we allow FP16 vreinterpret in ZVFHMIN consider we have vle FP16 already. It doesn't break anything in SPEC as there is no such vreinterpret insn. >From the user's perspective, it is reasonable to do some type convert between vfloat16 and v{u}int16 when only ZVFHMIN is enabled. This patch would like to add new test cases to make sure the RVV FP16 vreinterpret works well as expected. Signed-off-by: Pan Li gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: Add new cases. * gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Diito. --- .../riscv/rvv/base/zvfh-over-zvfhmin.c | 14 ++++++- .../riscv/rvv/base/zvfhmin-intrinsic.c | 38 ++++++++++++++++++- 2 files changed, 50 insertions(+), 2 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c index 2afc105e2da..d5bcdd5156a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c @@ -29,9 +29,21 @@ vfloat16m8_t test_vle16_v_f16m8(const float16_t *base, size_t vl) { return __riscv_vle16_v_f16m8(base, vl); } +vfloat16mf4_t test_vreinterpret_v_i16mf4_f16mf4(vint16mf4_t src) { + return __riscv_vreinterpret_v_i16mf4_f16mf4(src); +} + +vuint16m8_t test_vreinterpret_v_f16m8_u16m8(vfloat16m8_t src) { + return __riscv_vreinterpret_v_f16m8_u16m8(src); +} + /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 } } */ /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */ /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 4 } } */ /* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */ /* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */ -/* { dg-final { scan-assembler-times {vle16\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 3 } } */ +/* { dg-final { scan-assembler-times {vle16\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 4 } } */ +/* { dg-final { scan-assembler-times {vse16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 3 } } */ +/* { dg-final { scan-assembler-times {vl8re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 1 } } */ +/* { dg-final { scan-assembler-times {vs8r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c index f1a29b639e0..e56b2751d4c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c @@ -53,12 +53,48 @@ vfloat16m8_t test_vle16_v_f16m8(const float16_t *base, size_t vl) { return __riscv_vle16_v_f16m8(base, vl); } +vfloat16mf4_t test_vreinterpret_v_i16mf4_f16mf4(vint16mf4_t src) { + return __riscv_vreinterpret_v_i16mf4_f16mf4(src); +} + +vfloat16m8_t test_vreinterpret_v_i16m8_f16m8(vint16m8_t src) { + return __riscv_vreinterpret_v_i16m8_f16m8(src); +} + +vfloat16mf4_t test_vreinterpret_v_u16mf4_f16mf4(vuint16mf4_t src) { + return __riscv_vreinterpret_v_u16mf4_f16mf4(src); +} + +vfloat16m8_t test_vreinterpret_v_u16m8_f16m8(vuint16m8_t src) { + return __riscv_vreinterpret_v_u16m8_f16m8(src); +} + +vint16mf4_t test_vreinterpret_v_f16mf4_i16mf4(vfloat16mf4_t src) { + return __riscv_vreinterpret_v_f16mf4_i16mf4(src); +} + +vint16m8_t test_vreinterpret_v_f16m8_i16m8(vfloat16m8_t src) { + return __riscv_vreinterpret_v_f16m8_i16m8(src); +} + +vuint16mf4_t test_vreinterpret_v_f16mf4_u16mf4(vfloat16mf4_t src) { + return __riscv_vreinterpret_v_f16mf4_u16mf4(src); +} + +vuint16m8_t test_vreinterpret_v_f16m8_u16m8(vfloat16m8_t src) { + return __riscv_vreinterpret_v_f16m8_u16m8(src); +} + /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 } } */ /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 } } */ /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]} 2 } } */ /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]} 2 } } */ /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */ /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 7 } } */ /* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 5 } } */ /* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 5 } } */ -/* { dg-final { scan-assembler-times {vle16\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 4 } } */ +/* { dg-final { scan-assembler-times {vle16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 8 } } */ +/* { dg-final { scan-assembler-times {vse16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 7 } } */ +/* { dg-final { scan-assembler-times {vl8re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 4 } } */ +/* { dg-final { scan-assembler-times {vs8r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 6 } } */ -- 2.34.1