From: pan2.li@intel.com
To: gcc-patches@gcc.gnu.org
Cc: juzhe.zhong@rivai.ai, rdapp.gcc@gmail.com, jeffreyalaw@gmail.com,
pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com
Subject: [PATCH v1] RISC-V: Fix one typo in full-vec-movel test
Date: Tue, 13 Jun 2023 15:17:03 +0800 [thread overview]
Message-ID: <20230613071703.704283-1-pan2.li@intel.com> (raw)
From: Pan Li <pan2.li@intel.com>
This patch would like to fix one typo when checking assembly of
full-vec-movel.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c:
Adjust dg-do to comiple for asm checking.
---
.../gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c
index c1119cddee7..c32c31ecd69 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do compile } */
/* { dg-additional-options "-std=c99 -O3 -march=rv64gcv_zvl128b -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
#include <stdint-gcc.h>
--
2.34.1
next reply other threads:[~2023-06-13 7:17 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-13 7:17 pan2.li [this message]
2023-06-13 7:20 ` Robin Dapp
2023-06-13 7:21 ` juzhe.zhong
2023-06-13 7:23 ` Robin Dapp
2023-06-13 7:27 ` Li, Pan2
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