From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtpbg154.qq.com (smtpbg154.qq.com [15.184.224.54]) by sourceware.org (Postfix) with ESMTPS id 422173858289 for ; Tue, 13 Jun 2023 10:35:54 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 422173858289 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp71t1686652544tds5pmlc Received: from server1.localdomain ( [58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 13 Jun 2023 18:35:42 +0800 (CST) X-QQ-SSF: 01400000000000F0S000000A0000000 X-QQ-FEAT: LrCnY+iDm+P6Hkf8gBJdYb4saQNiV8811I6WCJ4++cpxU38ankkcGclWtjoz/ DIbOIJiVCUUZFi86lDPBc2za+G1km1MN/vTj+I17cQEG9i88eTfNhXmBZRZRTyP3AEtACmO R1fzxi7M5ZZGhFFUPUGyIYpuNDMpPWAmk3VVQYp++jmolUUH+Oa+uwlDg/gvVQ0jVifKLO3 94H7OB+bx5rXcRerIsjvlA+jxwkDkJyHqoxgJSEHBagPr7j1fqSzIvUZQ5zy7s18MbnBUGi goWl6jR2vcA1RY6hUzctNjRTpl2vg55HgK+VQwueBd/WJQnLXPz8y0I9Va0+EVcpQ/Rs/FF YhbMKuxpcxZLgoy9AT4WFZRMjFZjkFb1xgMpjn5W+q/aeeMUtTckVGHYpA9OX9Hf0C5FKdP ev6BxcBsYnw= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 14600497335018748754 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, palmer@dabbelt.com, palmer@rivosinc.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [PATCH V2] RISC-V: Add more SLP tests Date: Tue, 13 Jun 2023 18:35:41 +0800 Message-Id: <20230613103541.96476-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-10.2 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_SHORT,RCVD_IN_BARRACUDACENTRAL,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Juzhe-Zhong gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/partial/slp-10.c: New test. * gcc.target/riscv/rvv/autovec/partial/slp-11.c: New test. * gcc.target/riscv/rvv/autovec/partial/slp_run-10.c: New test. * gcc.target/riscv/rvv/autovec/partial/slp_run-11.c: New test. --- .../riscv/rvv/autovec/partial/slp-10.c | 32 ++++++++++++++++++ .../riscv/rvv/autovec/partial/slp-11.c | 33 +++++++++++++++++++ .../riscv/rvv/autovec/partial/slp_run-10.c | 33 +++++++++++++++++++ .../riscv/rvv/autovec/partial/slp_run-11.c | 33 +++++++++++++++++++ 4 files changed, 131 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-10.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-11.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-10.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-11.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-10.c new file mode 100644 index 00000000000..c5215611e53 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-10.c @@ -0,0 +1,32 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */ + +#include + +#define VEC_PERM(TYPE) \ + TYPE __attribute__ ((noinline, noclone)) \ + vec_slp_##TYPE (TYPE *restrict a, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + { \ + a[i * 2] += 10; \ + a[i * 2 + 1] += 17; \ + } \ + } + +#define TEST_ALL(T) \ + T (int8_t) \ + T (uint8_t) \ + T (int16_t) \ + T (uint16_t) \ + T (int32_t) \ + T (uint32_t) \ + T (int64_t) \ + T (uint64_t) + +TEST_ALL (VEC_PERM) + +/* { dg-final { scan-tree-dump-times "{ 10, 17, ... }" 8 "optimized" } } */ +/* This testcase is from aarch64 and floating-point operations are removed. + TODO: We will add floating-point operations back and make them as common test in the future. */ + diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-11.c new file mode 100644 index 00000000000..ccb5ab6831d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-11.c @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */ + +#include + +#define VEC_PERM(TYPE) \ + TYPE __attribute__ ((noinline, noclone)) \ + vec_slp_##TYPE (TYPE *restrict a, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + { \ + a[i * 4] += 41; \ + a[i * 4 + 1] += 25; \ + a[i * 4 + 2] += 31; \ + a[i * 4 + 3] += 62; \ + } \ + } + +#define TEST_ALL(T) \ + T (int8_t) \ + T (uint8_t) \ + T (int16_t) \ + T (uint16_t) \ + T (int32_t) \ + T (uint32_t) \ + T (int64_t) \ + T (uint64_t) + +TEST_ALL (VEC_PERM) + +/* { dg-final { scan-tree-dump "{ 41, 25, 31, 62, ... }" "optimized" } } */ +/* This testcase is from aarch64 and floating-point operations are removed. + TODO: We will add floating-point operations back and make them as common test in the future. */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-10.c new file mode 100644 index 00000000000..be95309a463 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-10.c @@ -0,0 +1,33 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include "slp-10.c" + +#define N (103 * 2) + +#define HARNESS(TYPE) \ + { \ + TYPE a[N], b[2] = { 10, 17 }; \ + for (unsigned int i = 0; i < N; ++i) \ + { \ + a[i] = i * 2 + i % 5; \ + asm volatile ("" ::: "memory"); \ + } \ + vec_slp_##TYPE (a, N / 2); \ + for (unsigned int i = 0; i < N; ++i) \ + { \ + TYPE orig = i * 2 + i % 5; \ + TYPE expected = orig + b[i % 2]; \ + if (a[i] != expected) \ + __builtin_abort (); \ + } \ + } + +int __attribute__ ((optimize (1))) +main (void) +{ + TEST_ALL (HARNESS) +} + +/* This testcase is from aarch64 and floating-point operations are removed. + TODO: We will add floating-point operations back and make them as common test in the future. */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-11.c new file mode 100644 index 00000000000..a48b18630e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-11.c @@ -0,0 +1,33 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include "slp-11.c" + +#define N (77 * 4) + +#define HARNESS(TYPE) \ + { \ + TYPE a[N], b[4] = { 41, 25, 31, 62 }; \ + for (unsigned int i = 0; i < N; ++i) \ + { \ + a[i] = i * 2 + i % 5; \ + asm volatile ("" ::: "memory"); \ + } \ + vec_slp_##TYPE (a, N / 4); \ + for (unsigned int i = 0; i < N; ++i) \ + { \ + TYPE orig = i * 2 + i % 5; \ + TYPE expected = orig + b[i % 4]; \ + if (a[i] != expected) \ + __builtin_abort (); \ + } \ + } + +int __attribute__ ((optimize (1))) +main (void) +{ + TEST_ALL (HARNESS) +} + +/* This testcase is from aarch64 and floating-point operations are removed. + TODO: We will add floating-point operations back and make them as common test in the future. */ -- 2.36.1