From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by sourceware.org (Postfix) with ESMTPS id 154703858D38 for ; Wed, 14 Jun 2023 00:59:04 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 154703858D38 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1686704344; x=1718240344; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=modHDbsalER+qOFi7bgDCMdPOnM7EDVhwRWEkgQ6dOU=; b=AT4wejs0EeeE42QOr0oWqIA+Sqkov8nCQv0pL87uyYbf2P5xNZdjMAkx BeMsu0SYbi6vsWFom5JuBGQBsQdjrv3/foaS6Q5bmB3U3bENZqcY0L6FD MWQfrhsqWKcuRvHRD4nmAzJEIaKV0QeTbQ5+KbdgpCBCuNmu+A5Aeptp1 UDyvU/sL9NfXBtasa3uCT9pYASqTbZeaPnmM9VBPmm2PlnOgtjJuM6Ql4 nRlE45Sg6vaHloEyoe3MOjCKvEM0dZ1kc/aDa8NqbtnesyYk6XWXZiN0W izBfjG1xiSBqCeiwCYidJ58FTzzp/Ads72/vx1pJy1dYmR66ta3HbVQIj g==; X-IronPort-AV: E=McAfee;i="6600,9927,10740"; a="360968225" X-IronPort-AV: E=Sophos;i="6.00,241,1681196400"; d="scan'208";a="360968225" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jun 2023 17:59:03 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10740"; a="715003601" X-IronPort-AV: E=Sophos;i="6.00,241,1681196400"; d="scan'208";a="715003601" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga007.fm.intel.com with ESMTP; 13 Jun 2023 17:59:00 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id EBC7B100514A; Wed, 14 Jun 2023 08:58:59 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, rdapp.gcc@gmail.com, jeffreyalaw@gmail.com, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Bugfix for vec_init repeating auto vectorization in RV32 Date: Wed, 14 Jun 2023 08:58:59 +0800 Message-Id: <20230614005859.960040-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_NUMSUBJECT,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Pan Li This patch would like to fix one bug exported by RV32 test case multiple_rgroup_run-2.c. The mask should be restricted by elen in vector, and the condition between the vmv.s.x and the vmv.v.x should take inner_bits_size rather than constants. Passed both the rv32 and rv64 riscv/rvv tests. Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv-v.cc (rvv_builder::get_merge_scalar_mask): Take elen instead of scalar BITS_PER_WORD. (expand_vector_init_merge_repeating_sequence): Use inner_bits_size instead of scaler BITS_PER_WORD. --- gcc/config/riscv/riscv-v.cc | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index fb970344521..9270e258ca3 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -399,10 +399,11 @@ rvv_builder::get_merge_scalar_mask (unsigned int index_in_pattern) const { unsigned HOST_WIDE_INT mask = 0; unsigned HOST_WIDE_INT base_mask = (1ULL << index_in_pattern); + unsigned int elen = TARGET_VECTOR_ELEN_64 ? 64 : 32; - gcc_assert (BITS_PER_WORD % npatterns () == 0); + gcc_assert (elen % npatterns () == 0); - int limit = BITS_PER_WORD / npatterns (); + int limit = elen / npatterns (); for (int i = 0; i < limit; i++) mask |= base_mask << (i * npatterns ()); @@ -1923,7 +1924,7 @@ expand_vector_init_merge_repeating_sequence (rtx target, rtx mask = gen_reg_rtx (mask_mode); rtx dup = gen_reg_rtx (dup_mode); - if (full_nelts <= BITS_PER_WORD) /* vmv.s.x. */ + if (full_nelts <= builder.inner_bits_size ()) /* vmv.s.x. */ { rtx ops[] = {dup, gen_scalar_move_mask (dup_mask_mode), RVV_VUNDEF (dup_mode), merge_mask}; @@ -1933,7 +1934,8 @@ expand_vector_init_merge_repeating_sequence (rtx target, else /* vmv.v.x. */ { rtx ops[] = {dup, force_reg (GET_MODE_INNER (dup_mode), merge_mask)}; - rtx vl = gen_int_mode (CEIL (full_nelts, BITS_PER_WORD), Pmode); + rtx vl = gen_int_mode (CEIL (full_nelts, builder.inner_bits_size ()), + Pmode); emit_nonvlmax_integer_move_insn (code_for_pred_broadcast (dup_mode), ops, vl); } -- 2.34.1