From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by sourceware.org (Postfix) with ESMTPS id CCCB83858414 for ; Wed, 14 Jun 2023 09:00:41 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org CCCB83858414 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1686733242; x=1718269242; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+0jgg3xmHwOEJJmZ8cmmH2aaXvbHcLBS8yRpsPpSpLA=; b=QHLlj99HggzlSq2k9vmQznxJ5GDMr3SlmAI+qs2F59CckTZPCrpq92t7 wiqyEI73yrlWl6Lcd3OP/dvW9ssoVdgtyChTlsX03lU4PKJIOcU+8y9Th K4c8HmaFpgQ+RusgdHAMQIpfbkdY1K8DLYzAeP1OiKVzgAwIDCX36OAYv N4AvLbtDhoOgGCJwtiLDnFOGBHOIzlj8TDkekea7e7cKM5D3AK1gYE+qA ADZJALSGBTJqvRm0KHFoz0heuszxcTt9GdaCSiJb5yoDO1Zwxf8r+AX/i Y7Te+t0OiLi+cbFVADZrqRLzKPJiTvM0XLrE0sSs1bn9sGPpEwB/Ysr3f w==; X-IronPort-AV: E=McAfee;i="6600,9927,10740"; a="343258838" X-IronPort-AV: E=Sophos;i="6.00,242,1681196400"; d="scan'208";a="343258838" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jun 2023 02:00:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10740"; a="1042117978" X-IronPort-AV: E=Sophos;i="6.00,242,1681196400"; d="scan'208";a="1042117978" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga005.fm.intel.com with ESMTP; 14 Jun 2023 02:00:37 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id B75D21005682; Wed, 14 Jun 2023 17:00:36 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, rdapp.gcc@gmail.com, jeffreyalaw@gmail.com, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v3] RISC-V: Bugfix for vec_init repeating auto vectorization in RV32 Date: Wed, 14 Jun 2023 17:00:35 +0800 Message-Id: <20230614090035.5470-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230614005859.960040-1-pan2.li@intel.com> References: <20230614005859.960040-1-pan2.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_NUMSUBJECT,KAM_SHORT,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Pan Li When constructing a vector mask from individual elements we wrongly assumed that we can broadcast BITS_PER_WORD (i.e. XLEN). The maximum is actually the vector element length (i.e. ELEN). This patch fixes this. After this patch, below failures on RV32 will be fixed. FAIL: gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c execution test FAIL: gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c execution test FAIL: gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c execution test FAIL: gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c execution test FAIL: gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c -std=c99 -O3 -ftree-vectorize --param riscv-autovec-preference=fixed-vlmax execution test Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv-v.cc (rvv_builder::get_merge_scalar_mask): Take elen instead of scalar BITS_PER_WORD. (expand_vector_init_merge_repeating_sequence): Use inner_bits_size instead of scaler BITS_PER_WORD. --- gcc/config/riscv/riscv-v.cc | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index e07d5c2901a..01f647bc0bd 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -399,10 +399,17 @@ rvv_builder::get_merge_scalar_mask (unsigned int index_in_pattern) const { unsigned HOST_WIDE_INT mask = 0; unsigned HOST_WIDE_INT base_mask = (1ULL << index_in_pattern); + /* Here we construct a mask pattern that will later be broadcast + to a vector register. The maximum broadcast size for vmv.v.x/vmv.s.x + is determined by the length of a vector element (ELEN) and not by + XLEN so make sure we do not exceed it. One example is -march=zve32* + which mandates ELEN == 32 but can be combined with -march=rv64 + with XLEN == 64. */ + unsigned int elen = TARGET_VECTOR_ELEN_64 ? 64 : 32; - gcc_assert (BITS_PER_WORD % npatterns () == 0); + gcc_assert (elen % npatterns () == 0); - int limit = BITS_PER_WORD / npatterns (); + int limit = elen / npatterns (); for (int i = 0; i < limit; i++) mask |= base_mask << (i * npatterns ()); @@ -1928,7 +1935,7 @@ expand_vector_init_merge_repeating_sequence (rtx target, rtx mask = gen_reg_rtx (mask_mode); rtx dup = gen_reg_rtx (dup_mode); - if (full_nelts <= BITS_PER_WORD) /* vmv.s.x. */ + if (full_nelts <= builder.inner_bits_size ()) /* vmv.s.x. */ { rtx ops[] = {dup, gen_scalar_move_mask (dup_mask_mode), RVV_VUNDEF (dup_mode), merge_mask}; @@ -1938,7 +1945,8 @@ expand_vector_init_merge_repeating_sequence (rtx target, else /* vmv.v.x. */ { rtx ops[] = {dup, force_reg (GET_MODE_INNER (dup_mode), merge_mask)}; - rtx vl = gen_int_mode (CEIL (full_nelts, BITS_PER_WORD), Pmode); + rtx vl = gen_int_mode (CEIL (full_nelts, builder.inner_bits_size ()), + Pmode); emit_nonvlmax_integer_move_insn (code_for_pred_broadcast (dup_mode), ops, vl); } -- 2.34.1