From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtpbg154.qq.com (smtpbg154.qq.com [15.184.224.54]) by sourceware.org (Postfix) with ESMTPS id 679D63857835 for ; Wed, 14 Jun 2023 10:34:51 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 679D63857835 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp74t1686738885tkgh6gdz Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 14 Jun 2023 18:34:44 +0800 (CST) X-QQ-SSF: 01400000000000B0E000000A0000000 X-QQ-FEAT: 0vfWcIgh24yrfCS4P/qARsmkWoOlckafJTkTiX/fmya7+e6oeitpTqAby6LgB elfU25s93QxULQcoOfJJgXkj5siOp6GaUFBUhltHFR/7wW/d7tpqItGVlHGoCC0orw+fbtT LuzXEcTizOiNHJmcAfgxHcj5lJNKyYDvd4T3UffouGIe0LIFaQTbfwhHbv0rz5T2ySFe02A PjvlIKfE2aokfWQBEtOxkDZW3HCzkFjZIYwPHBlJhgbITBhjcafv/URvu2ASth0tTmN0NTt UT7rXtWI5Hn09WqsIlUgPfSz9c3LOjFnaMxCUzHUbZ3gde9k4NPtfFG8Cz6urGhENjevCXt GS2fEB2N4+UVLLbLw8+K+/FGk82fpCisbySHwcmH6OL+jHwJ8TSq7iWrCGdXCWgBv4rrPKw X-QQ-GoodBg: 2 X-BIZMAIL-ID: 5730795690746033508 From: Lehua Ding To: gcc-patches@gcc.gnu.org, juzhe.zhong@rivai.ai Subject: [PATCH] RISC-V: Fix PR 110119 Date: Wed, 14 Jun 2023 18:34:44 +0800 Message-Id: <20230614103444.2179711-1-lehua.ding@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz5a-3 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_NUMSUBJECT,KAM_SHORT,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi, This patch fix the PR 110119. The reason for this bug is that in the case where the vector register is set to a fixed length (with `--param=riscv-autovec-preference=fixed-vlmax` option), TARGET_PASS_BY_REFERENCE thinks that variables of type vint32m1 can be passed through two scalar registers, but when GCC calls FUNCTION_VALUE (call function riscv_get_arg_info inside) it returns NULL_RTX. These two functions are not unified. The current treatment is to pass all vector arguments and returns through the function stack, and a new calling convention for vector registers will be added in the future. Best, Lehua gcc/ChangeLog: * config/riscv/riscv.cc (riscv_get_arg_info): Return NULL_RTX for vector mode (riscv_pass_by_reference): Return true for vector mode gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/p110119-1.c: New test. * gcc.target/riscv/rvv/base/p110119-2.c: New test. --- gcc/config/riscv/riscv.cc | 19 ++++++++----- .../gcc.target/riscv/rvv/base/p110119-1.c | 27 +++++++++++++++++++ .../gcc.target/riscv/rvv/base/p110119-2.c | 27 +++++++++++++++++++ 3 files changed, 67 insertions(+), 6 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/p110119-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/p110119-2.c diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index dd5361c2bd2a..be868c7b6127 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -3915,13 +3915,13 @@ riscv_get_arg_info (struct riscv_arg_info *info, const CUMULATIVE_ARGS *cum, riscv_pass_in_vector_p (type); } - /* TODO: Currently, it will cause an ICE for --param - riscv-autovec-preference=fixed-vlmax. So, we just return NULL_RTX here - let GCC generate loads/stores. Ideally, we should either warn the user not - to use an RVV vector type as function argument or support the calling - convention directly. */ - if (riscv_v_ext_mode_p (mode)) + /* All current vector arguments and return values are passed through the + function stack. Ideally, we should either warn the user not to use an RVV + vector type as function argument or support a calling convention + with better performance. */ + if (riscv_v_ext_mode_p (mode) || riscv_v_ext_tuple_mode_p (mode)) return NULL_RTX; + if (named) { riscv_aggregate_field fields[2]; @@ -4106,6 +4106,13 @@ riscv_pass_by_reference (cumulative_args_t cum_v, const function_arg_info &arg) return false; } + /* All current vector arguments and return values are passed through the + function stack. Ideally, we should either warn the user not to use an RVV + vector type as function argument or support a calling convention + with better performance. */ + if (riscv_v_ext_mode_p (arg.mode) || riscv_v_ext_tuple_mode_p (arg.mode)) + return true; + /* Pass by reference if the data do not fit in two integer registers. */ return !IN_RANGE (size, 0, 2 * UNITS_PER_WORD); } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/p110119-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/p110119-1.c new file mode 100644 index 000000000000..3583e06f1a8d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/p110119-1.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-skip-if "test rvv intrinsic" { *-*-* } { "*" } { "-march=rv*v*" } } */ + +#include "riscv_vector.h" + +typedef int8_t vnx2qi __attribute__ ((vector_size (2))); + +__attribute__ ((noipa)) vnx2qi +f_vnx2qi (int8_t a, int8_t b, int8_t *out) +{ + vnx2qi v = {a, b}; + return v; +} + +__attribute__ ((noipa)) vnx2qi +f_vnx2qi_2 (vnx2qi a, int8_t *out) +{ + return a; +} + +__attribute__ ((noipa)) vint32m1_t +f_vint32m1 (int8_t * a, int8_t *out) +{ + vint32m1_t v = *(vint32m1_t*)a; + return v; +} \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/p110119-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/p110119-2.c new file mode 100644 index 000000000000..1d12a610b677 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/p110119-2.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gczve32x --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-skip-if "test rvv intrinsic" { *-*-* } { "*" } { "-march=rv*v*" } } */ + +#include +#include "riscv_vector.h" + +__attribute__ ((noipa)) vint32m1x3_t +foo1 (int32_t *in, int vl) +{ + vint32m1x3_t v = __riscv_vlseg3e32_v_i32m1x3 (in, vl); + return v; +} + +__attribute__ ((noipa)) void +foo2 (vint32m1x3_t a, int32_t *out, int vl) +{ + __riscv_vsseg3e32_v_i32m1x3 (out, a, vl); +} + +__attribute__ ((noipa)) vint32m1x3_t +foo3 (vint32m1x3_t a, int32_t *out, int32_t *in, int vl) +{ + __riscv_vsseg3e32_v_i32m1x3 (out, a, vl); + vint32m1x3_t v = __riscv_vlseg3e32_v_i32m1x3 (in, vl); + return v; +} -- 2.36.3