From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from cstnet.cn (smtp25.cstnet.cn [159.226.251.25]) by sourceware.org (Postfix) with ESMTPS id 8F3ED385701B for ; Fri, 16 Jun 2023 04:32:50 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8F3ED385701B Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [39.170.88.238]) by APP-05 (Coremail) with SMTP id zQCowADH5wTq5YtkxPT6Ag--.41402S2; Fri, 16 Jun 2023 12:32:44 +0800 (CST) From: Liao Shihua To: gcc-patches@gcc.gnu.org Cc: kito.cheng@sifive.com, palmer@dabbelt.com, lazyparser@gmail.com, jiawei@iscas.ac.cn, jinma@linux.alibaba.com, juzhe.zhong@rivai.ai, shiyulong@iscas.ac.cn, chenyixuan@iscas.ac.cn, Liao Shihua Subject: [PATCH] Add bfloat16_t support for riscv Date: Fri, 16 Jun 2023 12:31:57 +0800 Message-Id: <20230616043157.1713-1-shihua@iscas.ac.cn> X-Mailer: git-send-email 2.38.1.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID:zQCowADH5wTq5YtkxPT6Ag--.41402S2 X-Coremail-Antispam: 1UD129KBjvJXoWfJFW3Jw4UZFW3Gw1rCFWxJFb_yoWDCFW8pF Z8G34avryrJFsag3Wfta45Ww13Jw4fKw1UZ3ykAryjya15XrWDtF1Duw4ftrWDXFZ8Arya 9rWjkrWjka1DA37anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUkK14x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26F1j6w1UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26F4j 6r4UJwA2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x0267AKxVW0oV Cq3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0 I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r 4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02628v n2kIc2xKxwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F4 0E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jw0_GFyl IxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxV AFwI0_Jr0_Gr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j 6r4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Jr0_GrUvcSsGvfC2KfnxnUUI43ZEXa7VUbXdbU UUUUU== X-Originating-IP: [39.170.88.238] X-CM-SenderInfo: xvklx33d6l2u1dvotugofq/1tbiCQQEEWSLtB-AjwAAsT X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_SHORT,SPF_HELO_PASS,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: x86_64/i686/AArch64 has for a few months working std::bfloat16_t=0D support, __bf16 there is no longer a storage only type, but can =0D be used for arithmetics and is supported in libgcc and libstdc++. =0D The patch adds similar support for RISC-V. __bf16 has been merged =0D in psABI. The compiler handles all operations with __bf16 by =0D converting to SFmode.=0D =0D gcc/ChangeLog:=0D =0D * config/riscv/iterators.md (ld):Add BFmode in iterators.=0D (sd):Ditto.=0D * config/riscv/riscv-builtins.cc (riscv_init_builtin_types):Add bfl= oat16_type_node in riscv.=0D * config/riscv/riscv-modes.def (FLOAT_MODE):Add BFmode in FLOAT_MOD= E.=0D (ADJUST_FLOAT_FORMAT):Ditto.=0D * config/riscv/riscv.cc (riscv_mangle_type):Add DF16b in mangle.=0D (riscv_scalar_mode_supported_p):Add BFmode in scalar_float_mode.=0D (riscv_libgcc_floating_mode_supported_p):Support BFmode in libgcc.= =0D * config/riscv/riscv.md (mode" ):Support BFmode in machine descript= ion.=0D (movbf): Support BFmode in softfloat.=0D (*movbf_softfloat):Ditto.=0D =0D libgcc/ChangeLog:=0D =0D * config/riscv/sfp-machine.h (_FP_NANFRAC_B):Define.=0D (_FP_NANSIGN_B):=0D * config/riscv/t-softfp32:Add trunc{tfbf dfbf sfbf hfbf}, extendbfs= f, floatdibf, floatundibf.=0D * config/riscv/t-softfp64:Add floattibf, floatuntibf.=0D =0D gcc/testsuite/ChangeLog:=0D =0D * gcc.target/riscv/__bf16-soft.c: New test.=0D =0D ---=0D gcc/config/riscv/iterators.md | 4 ++--=0D gcc/config/riscv/riscv-builtins.cc | 16 +++++++++++++++=0D gcc/config/riscv/riscv-modes.def | 2 ++=0D gcc/config/riscv/riscv.cc | 12 ++++++++---=0D gcc/config/riscv/riscv.md | 21 +++++++++++++++++++-=0D gcc/testsuite/gcc.target/riscv/__bf16-soft.c | 12 +++++++++++=0D libgcc/config/riscv/sfp-machine.h | 3 +++=0D libgcc/config/riscv/t-softfp32 | 7 ++++---=0D libgcc/config/riscv/t-softfp64 | 2 +-=0D 9 files changed, 69 insertions(+), 10 deletions(-)=0D create mode 100644 gcc/testsuite/gcc.target/riscv/__bf16-soft.c=0D =0D diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md= =0D index d374a10810c..c9148028ea3 100644=0D --- a/gcc/config/riscv/iterators.md=0D +++ b/gcc/config/riscv/iterators.md=0D @@ -87,13 +87,13 @@=0D (define_mode_attr default_load [(QI "lbu") (HI "lhu") (SI "lw") (DI "ld")]= )=0D =0D ;; Mode attribute for FP loads into integer registers.=0D -(define_mode_attr softload [(HF "lh") (SF "lw") (DF "ld")])=0D +(define_mode_attr softload [(BF "lh") (HF "lh") (SF "lw") (DF "ld")])=0D =0D ;; Instruction names for stores.=0D (define_mode_attr store [(QI "sb") (HI "sh") (SI "sw") (DI "sd") (HF "fsh"= ) (SF "fsw") (DF "fsd")])=0D =0D ;; Instruction names for FP stores from integer registers.=0D -(define_mode_attr softstore [(HF "sh") (SF "sw") (DF "sd")])=0D +(define_mode_attr softstore [(BF "sh") (HF "sh") (SF "sw") (DF "sd")])=0D =0D ;; This attribute gives the best constraint to use for registers of=0D ;; a given mode.=0D diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-bu= iltins.cc=0D index 79681d75962..398247a0ccb 100644=0D --- a/gcc/config/riscv/riscv-builtins.cc=0D +++ b/gcc/config/riscv/riscv-builtins.cc=0D @@ -194,6 +194,7 @@ static GTY(()) int riscv_builtin_decl_index[NUM_INSN_CO= DES];=0D riscv_builtin_decls[riscv_builtin_decl_index[(CODE)]]=0D =0D tree riscv_float16_type_node =3D NULL_TREE;=0D +tree riscv_bfloat16_type_node =3D NULL_TREE;=0D =0D /* Return the function type associated with function prototype TYPE. */=0D =0D @@ -237,6 +238,21 @@ riscv_init_builtin_types (void)=0D if (!maybe_get_identifier ("_Float16"))=0D lang_hooks.types.register_builtin_type (riscv_float16_type_node,=0D "_Float16");=0D +=0D + /* Provide the __bf16 type and bfloat16_type_node if needed. */=0D + if (!bfloat16_type_node)=0D + {=0D + riscv_bfloat16_type_node =3D make_node (REAL_TYPE);=0D + TYPE_PRECISION (riscv_bfloat16_type_node) =3D 16;=0D + SET_TYPE_MODE (riscv_bfloat16_type_node, BFmode);=0D + layout_type (riscv_bfloat16_type_node);=0D + }=0D + else=0D + riscv_bfloat16_type_node =3D bfloat16_type_node;=0D +=0D + if (!maybe_get_identifier ("__bf16"))=0D + lang_hooks.types.register_builtin_type (riscv_bfloat16_type_node,=0D + "__bf16");=0D }=0D =0D /* Implement TARGET_INIT_BUILTINS. */=0D diff --git a/gcc/config/riscv/riscv-modes.def b/gcc/config/riscv/riscv-mode= s.def=0D index 19a4f9fb3db..4bb03307840 100644=0D --- a/gcc/config/riscv/riscv-modes.def=0D +++ b/gcc/config/riscv/riscv-modes.def=0D @@ -21,6 +21,8 @@ along with GCC; see the file COPYING3. If not see=0D =0D FLOAT_MODE (HF, 2, ieee_half_format);=0D FLOAT_MODE (TF, 16, ieee_quad_format);=0D +FLOAT_MODE (BF, 2, 0);=0D +ADJUST_FLOAT_FORMAT (BF, &arm_bfloat_half_format);=0D =0D /* Vector modes. */=0D =0D diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc=0D index e5ae4e81b7a..d5b1350d4bf 100644=0D --- a/gcc/config/riscv/riscv.cc=0D +++ b/gcc/config/riscv/riscv.cc=0D @@ -7155,8 +7155,14 @@ static const char *=0D riscv_mangle_type (const_tree type)=0D {=0D /* Half-precision float, _Float16 is "DF16_". */=0D - if (SCALAR_FLOAT_TYPE_P (type) && TYPE_PRECISION (type) =3D=3D 16)=0D + /* Bfloat, __bf16 is "DF16b" */=0D + if (TREE_CODE (type) =3D=3D REAL_TYPE && TYPE_PRECISION (type) =3D=3D 16= )=0D + {=0D + if (TYPE_MODE (type) =3D=3D BFmode)=0D + return "DF16b";=0D + else=0D return "DF16_";=0D + }=0D =0D /* Mangle all vector type for vector extension. */=0D /* The mangle name follows the rule of RVV LLVM=0D @@ -7177,7 +7183,7 @@ riscv_mangle_type (const_tree type)=0D static bool=0D riscv_scalar_mode_supported_p (scalar_mode mode)=0D {=0D - if (mode =3D=3D HFmode)=0D + if (mode =3D=3D HFmode || mode =3D=3D BFmode)=0D return true;=0D else=0D return default_scalar_mode_supported_p (mode);=0D @@ -7189,7 +7195,7 @@ riscv_scalar_mode_supported_p (scalar_mode mode)=0D static bool=0D riscv_libgcc_floating_mode_supported_p (scalar_float_mode mode)=0D {=0D - if (mode =3D=3D HFmode)=0D + if (mode =3D=3D HFmode || BFmode)=0D return true;=0D else=0D return default_libgcc_floating_mode_supported_p (mode);=0D diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md=0D index d8e935cb934..77b52862bbd 100644=0D --- a/gcc/config/riscv/riscv.md=0D +++ b/gcc/config/riscv/riscv.md=0D @@ -169,7 +169,7 @@=0D (const_string "unknown"))=0D =0D ;; Main data type used by the insn=0D -(define_attr "mode" "unknown,none,QI,HI,SI,DI,TI,HF,SF,DF,TF,=0D +(define_attr "mode" "unknown,none,QI,HI,SI,DI,TI,BF,HF,SF,DF,TF,=0D VNx1BI,VNx2BI,VNx4BI,VNx8BI,VNx16BI,VNx32BI,VNx64BI,VNx128BI,=0D VNx1QI,VNx2QI,VNx4QI,VNx8QI,VNx16QI,VNx32QI,VNx64QI,VNx128QI,=0D VNx1HI,VNx2HI,VNx4HI,VNx8HI,VNx16HI,VNx32HI,VNx64HI,=0D @@ -1744,6 +1744,25 @@=0D [(set_attr "move_type" "fmove,move,load,store,mtc,mfc")=0D (set_attr "mode" "HF")])=0D =0D +;; 16-bit bfloating point moves=0D +(define_expand "movbf"=0D + [(set (match_operand:BF 0 "")=0D + (match_operand:BF 1 ""))]=0D + ""=0D +{=0D + if (riscv_legitimize_move (BFmode, operands[0], operands[1]))=0D + DONE;=0D +})=0D +=0D +(define_insn "*movbf_softfloat"=0D + [(set (match_operand:BF 0 "nonimmediate_operand" "=3Df, r,r,m,*f,*r")=0D + (match_operand:BF 1 "move_operand" " f,Gr,m,r,*r,*f"))]=0D + "(register_operand (operands[0], BFmode)=0D + || reg_or_0_operand (operands[1], BFmode))"=0D + { return riscv_output_move (operands[0], operands[1]); }=0D + [(set_attr "move_type" "fmove,move,load,store,mtc,mfc")=0D + (set_attr "mode" "BF")])=0D +=0D ;;=0D ;; ....................=0D ;;=0D diff --git a/gcc/testsuite/gcc.target/riscv/__bf16-soft.c b/gcc/testsuite/g= cc.target/riscv/__bf16-soft.c=0D new file mode 100644=0D index 00000000000..eca98a799d0=0D --- /dev/null=0D +++ b/gcc/testsuite/gcc.target/riscv/__bf16-soft.c=0D @@ -0,0 +1,12 @@=0D +/* { dg-do compile } */=0D +/* { dg-options "-march=3Drv64if -mabi=3Dlp64f -O" } */=0D +=0D +__bf16 test_soft_add (__bf16 a, __bf16 b)=0D +{=0D + /* Make sure fadd.s invoked here. */=0D + /* { dg-final { scan-assembler-times "call\t__extendbfsf2" 2 } } */=0D + return a + b;=0D + /* { dg-final { scan-assembler-times "fadd.s" 1 } } */=0D + /* { dg-final { scan-assembler-times "call\t__truncsfbf2" 1 } } */=0D +}=0D +=0D diff --git a/libgcc/config/riscv/sfp-machine.h b/libgcc/config/riscv/sfp-ma= chine.h=0D index ded594d75d8..2ed7cbf3a30 100644=0D --- a/libgcc/config/riscv/sfp-machine.h=0D +++ b/libgcc/config/riscv/sfp-machine.h=0D @@ -41,6 +41,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. = If not, see=0D #define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_2_udiv(D,R,X,Y)=0D #define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_4_udiv(Q,R,X,Y)=0D =0D +#define _FP_NANFRAC_B _FP_QNANBIT_B=0D #define _FP_NANFRAC_H _FP_QNANBIT_H=0D #define _FP_NANFRAC_S _FP_QNANBIT_S=0D #define _FP_NANFRAC_D _FP_QNANBIT_D, 0=0D @@ -64,6 +65,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. = If not, see=0D #define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_1_udiv_norm(D,R,X,Y)=0D #define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_2_udiv(Q,R,X,Y)=0D =0D +#define _FP_NANFRAC_B _FP_QNANBIT_B=0D #define _FP_NANFRAC_H _FP_QNANBIT_H=0D #define _FP_NANFRAC_S _FP_QNANBIT_S=0D #define _FP_NANFRAC_D _FP_QNANBIT_D=0D @@ -82,6 +84,7 @@ typedef unsigned int UTItype __attribute__ ((mode (TI)));= =0D typedef int __gcc_CMPtype __attribute__ ((mode (__libgcc_cmp_return__)));= =0D #define CMPtype __gcc_CMPtype=0D =0D +#define _FP_NANSIGN_B 0=0D #define _FP_NANSIGN_H 0=0D #define _FP_NANSIGN_S 0=0D #define _FP_NANSIGN_D 0=0D diff --git a/libgcc/config/riscv/t-softfp32 b/libgcc/config/riscv/t-softfp3= 2=0D index 55261f98383..25ac9f07541 100644=0D --- a/libgcc/config/riscv/t-softfp32=0D +++ b/libgcc/config/riscv/t-softfp32=0D @@ -42,7 +42,8 @@ softfp_extras :=3D divsf3 divdf3 divtf3=0D =0D endif=0D =0D -softfp_extensions +=3D hfsf hfdf hftf=0D -softfp_truncations +=3D tfhf dfhf sfhf=0D +softfp_extensions +=3D hfsf hfdf hftf bfsf=0D +softfp_truncations +=3D tfhf dfhf sfhf hfbf sfbf dfbf tfbf=0D softfp_extras +=3D fixhfsi fixhfdi fixunshfsi fixunshfdi \=0D - floatsihf floatdihf floatunsihf floatundihf=0D + floatsihf floatdihf floatunsihf floatundihf \=0D + floatdibf floatundibf=0D diff --git a/libgcc/config/riscv/t-softfp64 b/libgcc/config/riscv/t-softfp6= 4=0D index c87d242d5c3..6f8c21352b6 100644=0D --- a/libgcc/config/riscv/t-softfp64=0D +++ b/libgcc/config/riscv/t-softfp64=0D @@ -1,4 +1,4 @@=0D include $(srcdir)/config/riscv/t-softfp32=0D =0D softfp_int_modes +=3D ti=0D -softfp_extras +=3D fixhfti fixunshfti floattihf floatuntihf=0D +softfp_extras +=3D fixhfti fixunshfti floattihf floatuntihf floattibf floa= tuntibf=0D -- =0D 2.34.1=0D =0D