From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from zg8tmtyylji0my4xnjqumte4.icoremail.net (zg8tmtyylji0my4xnjqumte4.icoremail.net [162.243.164.118]) by sourceware.org (Postfix) with ESMTP id 243B73858C62 for ; Sun, 25 Jun 2023 03:08:41 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 243B73858C62 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=eswincomputing.com Received: from host014-ubuntu-1804.lxd (unknown [10.12.130.31]) by app2 (Coremail) with SMTP id EggMCgCHzZO2r5dk5PgpAA--.48860S4; Sun, 25 Jun 2023 11:08:38 +0800 (CST) From: Li Xu To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, juzhe.zhong@rivai.ai, Li Xu Subject: [PATCH] RISC-V: force arg and target to reg rtx under -O0 Date: Sun, 25 Jun 2023 03:08:37 +0000 Message-Id: <20230625030837.23389-1-xuli1@eswincomputing.com> X-Mailer: git-send-email 2.17.1 X-CM-TRANSID:EggMCgCHzZO2r5dk5PgpAA--.48860S4 X-Coremail-Antispam: 1UD129KBjvJXoWxGw48GryfCF15CrWkCFW3Wrg_yoW5WF4fpa 1DGr42yrWrJFZ3Gwn3trWxGr45Krs3W3s5Zw1fZw17Ca15JrZIqan8ta42yFsxWF13Wryx C3Wfu345Z3W5tw7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUk214x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26w1j6s0DM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc CE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E 2Ix0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJV W8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lc2xSY4AK6svPMxAI w28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr 4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwIxG rwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8Jw CI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2 z280aVCY1x0267AKxVWUJVW8JbIYCTnIWIevJa73UjIFyTuYvjfUoOJ5UUUUU X-CM-SenderInfo: 50xoxi46hv4xpqfrz1xxwl0woofrz/ X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_NUMSUBJECT,KAM_SHORT,RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE,WEIRD_PORT autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: arg and target should be expanded to reg rtx during expand pass. Consider this following case: void test_vlmul_ext_v_i8mf8_i8mf4(vint8mf8_t op1) { vint8mf4_t res = __riscv_vlmul_ext_v_i8mf8_i8mf4(op1); } Compilation fails with: test.c: In function 'test_vlmul_ext_v_i8mf8_i8mf4': test.c:5:1: error: unrecognizable insn: 5 | } | ^ (insn 30 29 0 2 (set (mem/c:VNx2QI (reg/f:DI 143) [0 x+0 S[2, 2] A32]) (mem/c:VNx2QI (reg/f:DI 148) [0 op1+0 S[2, 2] A16])) "test.c":4:18 -1 (nil)) during RTL pass: vregs test.c:5:1: internal compiler error: in extract_insn, at recog.cc:2791 0x7c61b8 _fatal_insn(char const*, rtx_def const*, char const*, int, char const*) ../.././riscv-gcc/gcc/rtl-error.cc:108 0x7c61d7 _fatal_insn_not_found(rtx_def const*, char const*, int, char const*) ../.././riscv-gcc/gcc/rtl-error.cc:116 0xed58a7 extract_insn(rtx_insn*) ../.././riscv-gcc/gcc/recog.cc:2791 0xb7f789 instantiate_virtual_regs_in_insn ../.././riscv-gcc/gcc/function.cc:1611 0xb7f789 instantiate_virtual_regs ../.././riscv-gcc/gcc/function.cc:1984 gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc: force arg and target to reg rtx. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vlmul_ext-2.c: New test. --- gcc/config/riscv/riscv-vector-builtins-bases.cc | 5 ++++- gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-2.c | 8 ++++++++ 2 files changed, 12 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-2.c diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index c6c53dc13a5..f135f7971fa 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -1567,7 +1567,10 @@ public: { tree arg = CALL_EXPR_ARG (e.exp, 0); rtx src = expand_normal (arg); - emit_insn (gen_rtx_SET (gen_lowpart (e.vector_mode (), e.target), src)); + if (MEM_P (e.target)) + e.target = force_reg (GET_MODE (e.target), e.target); + emit_insn (gen_rtx_SET (gen_lowpart (e.vector_mode (), e.target), + MEM_P (src) ? force_reg (GET_MODE (src), src) : src)); return e.target; } }; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-2.c new file mode 100644 index 00000000000..2b088b53546 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-2.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O0" } */ + +#include "riscv_vector.h" + +void test_vlmul_ext_v_i8mf8_i8mf4(vint8mf8_t op1) { + vint8mf4_t res = __riscv_vlmul_ext_v_i8mf8_i8mf4(op1); +} -- 2.17.1