From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by sourceware.org (Postfix) with ESMTPS id B428F3858CD1 for ; Wed, 5 Jul 2023 07:02:35 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B428F3858CD1 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1688540555; x=1720076555; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZHI3OjKouGXdT7pSpU6MSzZf6AmJjWInzkMEA5keCUc=; b=cy9lwS/CmaddZhZvpY4eNV40Y3iQC+U9q3qGL9+KeaM8FjbdvsUXZ4Nd FyFHC7Wmziyd7UQiVUvzPLSMMhFX5bvKgdijJTyoyTSg8mcS2BG/Tniac bzANmfbEDpxdEY7wvhL6SmQK+Fk7632XHSx9iE+sTtSCgVgsbCJOLurW+ kOG6bhZv3iKD7cyyc7++aC5CN5zLWA+vZZeA4KhuyvKEmWsVz9k7fGaI4 sQ0L8LAH4iqcowpvVkuWrYEuFWtYiIIwHrxHu0fj/i20h+m5wace30jVF 61si5WlENeEyFARXroRuARoZoFSQb/YoSQAbOm//Klwjc6h0uZftnRdI1 Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10761"; a="342858092" X-IronPort-AV: E=Sophos;i="6.01,182,1684825200"; d="scan'208";a="342858092" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jul 2023 00:02:33 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10761"; a="669298155" X-IronPort-AV: E=Sophos;i="6.01,182,1684825200"; d="scan'208";a="669298155" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by orsmga003.jf.intel.com with ESMTP; 05 Jul 2023 00:02:31 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id 47D5D10119E6; Wed, 5 Jul 2023 15:02:30 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, rdapp.gcc@gmail.com, jeffreyalaw@gmail.com, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v4] RISC-V: Fix one bug for floating-point static frm Date: Wed, 5 Jul 2023 15:02:23 +0800 Message-Id: <20230705070223.806580-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,SPF_HELO_PASS,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Pan Li This patch would like to fix one bug to align below items of spec. 1. By default, the RVV floating-point will take dyn mode. 2. DYN is invalid in FRM register for RVV floating-point. When mode switching the function entry and exit, it will take DYN as the frm mode. Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv.cc (riscv_emit_mode_set): Avoid emit insn when FRM_MODE_DYN. (riscv_mode_entry): Take FRM_MODE_DYN as entry mode. (riscv_mode_exit): Likewise for exit mode. (riscv_mode_needed): Likewise for needed mode. (riscv_mode_after): Likewise for after mode. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-frm-insert-6.c: New test. --- gcc/config/riscv/riscv.cc | 16 +++++++--- .../riscv/rvv/base/float-point-frm-insert-6.c | 31 +++++++++++++++++++ 2 files changed, 42 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index e4dc8115e69..4db32de5696 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -7670,7 +7670,7 @@ riscv_emit_mode_set (int entity, int mode, int prev_mode, emit_insn (gen_vxrmsi (gen_int_mode (mode, SImode))); break; case RISCV_FRM: - if (mode != FRM_MODE_NONE && mode != prev_mode) + if (mode != FRM_MODE_DYN && mode != prev_mode) { rtx scaler = gen_reg_rtx (SImode); rtx imm = gen_int_mode (mode, SImode); @@ -7697,7 +7697,9 @@ riscv_mode_needed (int entity, rtx_insn *insn) case RISCV_VXRM: return code >= 0 ? get_attr_vxrm_mode (insn) : VXRM_MODE_NONE; case RISCV_FRM: - return code >= 0 ? get_attr_frm_mode (insn) : FRM_MODE_NONE; + /* According to RVV 1.0 spec, all vector floating-point operations use + the dynamic rounding mode in the frm register. */ + return code >= 0 ? get_attr_frm_mode (insn) : FRM_MODE_DYN; default: gcc_unreachable (); } @@ -7757,7 +7759,7 @@ riscv_mode_after (int entity, int mode, rtx_insn *insn) case RISCV_FRM: return riscv_entity_mode_after (FRM_REGNUM, insn, mode, (int (*)(rtx_insn *)) get_attr_frm_mode, - FRM_MODE_NONE); + FRM_MODE_DYN); default: gcc_unreachable (); } @@ -7774,7 +7776,9 @@ riscv_mode_entry (int entity) case RISCV_VXRM: return VXRM_MODE_NONE; case RISCV_FRM: - return FRM_MODE_NONE; + /* According to RVV 1.0 spec, all vector floating-point operations use + the dynamic rounding mode in the frm register. */ + return FRM_MODE_DYN; default: gcc_unreachable (); } @@ -7791,7 +7795,9 @@ riscv_mode_exit (int entity) case RISCV_VXRM: return VXRM_MODE_NONE; case RISCV_FRM: - return FRM_MODE_NONE; + /* According to RVV 1.0 spec, all vector floating-point operations use + the dynamic rounding mode in the frm register. */ + return FRM_MODE_DYN; default: gcc_unreachable (); } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c new file mode 100644 index 00000000000..6d896e0953e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +typedef float float32_t; + +vfloat32m1_t +test_riscv_vfadd_vv_f32m1_rm (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) { + return __riscv_vfadd_vv_f32m1_rm (op1, op2, 7, vl); +} + +vfloat32m1_t +test_vfadd_vv_f32m1_m_rm(vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2, + size_t vl) { + return __riscv_vfadd_vv_f32m1_m_rm(mask, op1, op2, 7, vl); +} + +vfloat32m1_t +test_vfadd_vf_f32m1_rm(vfloat32m1_t op1, float32_t op2, size_t vl) { + return __riscv_vfadd_vf_f32m1_rm(op1, op2, 7, vl); +} + +vfloat32m1_t +test_vfadd_vf_f32m1_m_rm(vbool32_t mask, vfloat32m1_t op1, float32_t op2, + size_t vl) { + return __riscv_vfadd_vf_f32m1_m_rm(mask, op1, op2, 7, vl); +} + +/* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 4 } } */ +/* { dg-final { scan-assembler-not {fsrm\s+[ax][0-9]+,\s*[ax][0-9]+} } } */ -- 2.34.1