From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by sourceware.org (Postfix) with ESMTPS id 1331E385840B for ; Wed, 12 Jul 2023 15:07:23 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 1331E385840B Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1689174444; x=1720710444; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=Xtl2Fh9fcxNXHunBgSg8b1dBEa7RaDA3qN4CML25hBU=; b=kQhMRPMF9FjjMfczWLh/lazwTI1HeguxOGGn6tMynoHj+KLUszlIEg8w 3QhhFh4FXCtqtAlsgF4ek4/HUm9QBEEYi7lBq/OkoFwKUyo79l7o35+R5 2Bwfk3wnpkSMQbHZjcIN5fWymnHt3u6gILFy6o2kAjc2CU6i2yfrmzXoZ a1NfR+csUdq33inxdj2lcWjbGs27cjzKtb9RPeySOC7hIlvLjnZH2Tqgb u/JkEqaPn7OOKhDX/Ujr8b5ccmLaW5VrtG22PrxfbsM04LaglofS2dMdV nxyxb2a8GZ6izGUDRFd1REBvjWBwu+gqFtmHZFn6C+p7nGmsc7eplUGzJ A==; X-IronPort-AV: E=McAfee;i="6600,9927,10769"; a="367533709" X-IronPort-AV: E=Sophos;i="6.01,200,1684825200"; d="scan'208";a="367533709" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2023 08:03:10 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10769"; a="721531603" X-IronPort-AV: E=Sophos;i="6.01,199,1684825200"; d="scan'208";a="721531603" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by orsmga002.jf.intel.com with ESMTP; 12 Jul 2023 08:03:08 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id 860D01007EA8; Wed, 12 Jul 2023 23:03:07 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, rdapp.gcc@gmail.com, jeffreyalaw@gmail.com, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Add more tests for RVV floating-point FRM. Date: Wed, 12 Jul 2023 23:03:02 +0800 Message-Id: <20230712150302.3517511-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-1.0 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE,UNWANTED_LANGUAGE_BODY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Pan Li Add more test cases include both the asm check and run for RVV FRM. Signed-off-by: Pan Li gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-frm-insert-10.c: New test. * gcc.target/riscv/rvv/base/float-point-frm-insert-7.c: New test. * gcc.target/riscv/rvv/base/float-point-frm-insert-8.c: New test. * gcc.target/riscv/rvv/base/float-point-frm-insert-9.c: New test. * gcc.target/riscv/rvv/base/float-point-frm-run-1.c: New test. * gcc.target/riscv/rvv/base/float-point-frm-run-2.c: New test. * gcc.target/riscv/rvv/base/float-point-frm-run-3.c: New test. --- .../rvv/base/float-point-frm-insert-10.c | 23 ++++++ .../riscv/rvv/base/float-point-frm-insert-7.c | 29 +++++++ .../riscv/rvv/base/float-point-frm-insert-8.c | 27 +++++++ .../riscv/rvv/base/float-point-frm-insert-9.c | 24 ++++++ .../riscv/rvv/base/float-point-frm-run-1.c | 79 +++++++++++++++++++ .../riscv/rvv/base/float-point-frm-run-2.c | 71 +++++++++++++++++ .../riscv/rvv/base/float-point-frm-run-3.c | 73 +++++++++++++++++ 7 files changed, 326 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-10.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-9.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-3.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-10.c new file mode 100644 index 00000000000..d35ee6d2131 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-10.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +void +test_float_point_frm_static (float *out, vfloat32m1_t op1, vfloat32m1_t op2, + size_t vl) +{ + asm volatile ( + "addi %0, %0, 0x12" + :"=r"(vl) + : + : + ); + + vfloat32m1_t result = __riscv_vfadd_vv_f32m1_rm (op1, op2, 2, vl); + result = __riscv_vfadd_vv_f32m1_rm (op1, result, 3, vl); + *(vfloat32m1_t *)out = result; +} + +/* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[ax][0-9]+,\s*[ax][0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-7.c new file mode 100644 index 00000000000..7b1602fd509 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-7.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +size_t __attribute__ ((noinline)) +normalize_vl (size_t vl) +{ + if (vl % 4 == 0) + return vl; + + return ((vl / 4) + 1) * 4; +} + +void +test_float_point_frm_static (float *out, vfloat32m1_t op1, vfloat32m1_t op2, + size_t vl) +{ + vfloat32m1_t result = __riscv_vfadd_vv_f32m1_rm (op1, op2, 2, vl); + + vl = normalize_vl (vl); + + result = __riscv_vfadd_vv_f32m1_rm (op1, result, 3, vl); + + *(vfloat32m1_t *)out = result; +} + +/* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[ax][0-9]+,\s*[ax][0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-8.c new file mode 100644 index 00000000000..37481ddac38 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-8.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +size_t __attribute__ ((noinline)) +normalize_vl (size_t vl) +{ + if (vl % 4 == 0) + return vl; + + return ((vl / 4) + 1) * 4; +} + +void +test_float_point_frm_static (float *out, vfloat32m1_t op1, vfloat32m1_t op2, + size_t vl) +{ + vl = normalize_vl (vl); + + vfloat32m1_t result = __riscv_vfadd_vv_f32m1_rm (op1, op2, 2, vl); + + *(vfloat32m1_t *)out = result; +} + +/* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[ax][0-9]+,\s*[ax][0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-9.c new file mode 100644 index 00000000000..7ae834ad531 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-9.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +void +test_float_point_frm_static (float *out, vfloat32m1_t op1, vfloat32m1_t op2, + size_t vl) +{ + vfloat32m1_t result = __riscv_vfadd_vv_f32m1_rm (op1, op2, 2, vl); + + asm volatile ( + "fsrmi 4" + : + : + :"frm" + ); + + result = __riscv_vfadd_vv_f32m1_rm (op1, result, 3, vl); + *(vfloat32m1_t *)out = result; +} + +/* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[ax][0-9]+,\s*[ax][0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c new file mode 100644 index 00000000000..210c49c5e8d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c @@ -0,0 +1,79 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-options "-O3 -Wno-psabi" } */ + +#include "riscv_vector.h" +#include +#include + +static int +get_frm () +{ + int frm = -1; + + __asm__ volatile ( + "frrm %0" + :"=r"(frm) + : + : + ); + + return frm; +} + +static void +set_frm (int frm) +{ + __asm__ volatile ( + "fsrm %0" + : + :"r"(frm) + : + ); +} + +static inline void +assert_equal (int a, int b, char *message) +{ + if (a != b) + { + printf (message); + __builtin_abort (); + } +} + +vfloat32m1_t __attribute__ ((noinline)) +test_float_point_frm_run (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) +{ + set_frm (0); + + vfloat32m1_t result; + + result = __riscv_vfadd_vv_f32m1_rm (op1, result, 1, vl); + assert_equal (1, get_frm (), "The value of frm register should be 1."); + + result = __riscv_vfadd_vv_f32m1_rm (op1, result, 2, vl); + assert_equal (2, get_frm (), "The value of frm register should be 2."); + + result = __riscv_vfadd_vv_f32m1_rm (op1, result, 3, vl); + assert_equal (3, get_frm (), "The value of frm register should be 3."); + + result = __riscv_vfadd_vv_f32m1_rm (op1, result, 4, vl); + assert_equal (4, get_frm (), "The value of frm register should be 4."); + + result = __riscv_vfadd_vv_f32m1_rm (op1, result, 0, vl); + assert_equal (0, get_frm (), "The value of frm register should be 0."); + + return result; +} + +int +main () +{ + size_t vl = 8; + vfloat32m1_t op1; + vfloat32m1_t op2; + + test_float_point_frm_run (op1, op2, vl); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-2.c new file mode 100644 index 00000000000..0b26c459955 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-2.c @@ -0,0 +1,71 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-options "-O3 -Wno-psabi" } */ + +#include "riscv_vector.h" +#include +#include + +static int +get_frm () +{ + int frm = -1; + + __asm__ volatile ( + "frrm %0" + :"=r"(frm) + : + : + ); + + return frm; +} + +static void +set_frm (int frm) +{ + __asm__ volatile ( + "fsrm %0" + : + :"r"(frm) + : + ); +} + +static inline void +assert_equal (int a, int b, char *message) +{ + if (a != b) + { + fprintf (stdout, "%s, but get %d != %d\n", message, a, b); + __builtin_abort (); + } +} + +vfloat32m1_t __attribute__ ((noinline)) +test_float_point_frm_run (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) +{ + set_frm (0); + + vfloat32m1_t result = {}; + + result = __riscv_vfadd_vv_f32m1_rm (op1, result, 1, vl); + result = __riscv_vfadd_vv_f32m1_rm (op1, result, 2, vl); + result = __riscv_vfadd_vv_f32m1_rm (op1, result, 4, vl); + + assert_equal (4, get_frm (), "The value of frm register should be 4."); + + return result; +} + +int +main () +{ + size_t vl = 8; + vfloat32m1_t op1 = {}; + vfloat32m1_t op2 = {}; + + test_float_point_frm_run (op1, op2, vl); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-3.c new file mode 100644 index 00000000000..4c17e54b78a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-3.c @@ -0,0 +1,73 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-options "-O3 -Wno-psabi" } */ + +#include "riscv_vector.h" +#include +#include + +static int +get_frm () +{ + int frm = -1; + + __asm__ volatile ( + "frrm %0" + :"=r"(frm) + : + : + ); + + return frm; +} + +static void +set_frm (int frm) +{ + __asm__ volatile ( + "fsrm %0" + : + :"r"(frm) + : + ); +} + +static inline void +assert_equal (int a, int b, char *message) +{ + if (a != b) + { + fprintf (stdout, "%s, but get %d != %d\n", message, a, b); + __builtin_abort (); + } +} + +vfloat32m1_t __attribute__ ((noinline)) +test_float_point_frm_run (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) +{ + set_frm (0); + + vfloat32m1_t result = {}; + + result = __riscv_vfadd_vv_f32m1_rm (op1, result, 4, vl); + + result = __riscv_vfadd_vv_f32m1 (op1, result, vl); + result = __riscv_vfadd_vv_f32m1 (op1, result, vl); + + assert_equal (4, get_frm (), "The value of frm register should be 4."); + + return result; +} + +int +main () +{ + size_t vl = 8; + vfloat32m1_t op1 = {}; + vfloat32m1_t op2 = {}; + + test_float_point_frm_run (op1, op2, vl); + + return 0; +} + + -- 2.34.1