From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by sourceware.org (Postfix) with ESMTPS id 6C06C3858C1F for ; Thu, 13 Jul 2023 06:18:58 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 6C06C3858C1F Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1689229138; x=1720765138; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ktdpsfCnMZ3LwlLsjWsS0Ou2kp7/5yiFCo70JYA7a28=; b=XFktwij/CRLy8GL2e9JGki0urO4tFZheucuOlbQqFmAI9nGMYoO0m44D H42P65IG/H5erdb6n94SaZ2OYVqoeYH+Lj/Ues4trLHp5N3auSQhkpezE JPX5Zd9OkBn5AO/FlzV3d13uKtXNBoIoqQDxXWxDgQur4RjP+gZhDblIu kA924hi84QgZKXXnWM+vd8pE6TShXtiFrIlo5csGukh5wCmNJJkPNVLk8 0+/SaxYDlmq6p/4P7YqwezMH9lZbK1qgpKAjUEyFinyYI1AHAWCdRxUG2 sxTr6XYsyMhHfCnUKf+qZV0J5DFlJrlDl6Omtri+eeoC2w48fjkl5Chpy A==; X-IronPort-AV: E=McAfee;i="6600,9927,10769"; a="345411774" X-IronPort-AV: E=Sophos;i="6.01,201,1684825200"; d="scan'208";a="345411774" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2023 23:18:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10769"; a="835453196" X-IronPort-AV: E=Sophos;i="6.01,201,1684825200"; d="scan'208";a="835453196" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga002.fm.intel.com with ESMTP; 12 Jul 2023 23:18:47 -0700 Received: from yanzhang-dev.sh.intel.com (yanzhang-dev.sh.intel.com [10.239.159.126]) by shvmail03.sh.intel.com (Postfix) with ESMTP id D3DB610056EF; Thu, 13 Jul 2023 14:18:46 +0800 (CST) From: yanzhang.wang@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@sifive.com, pan2.li@intel.com, yanzhang.wang@intel.com Subject: [PATCH] RISCV: Add -m(no)-omit-leaf-frame-pointer support. Date: Thu, 13 Jul 2023 14:12:08 +0800 Message-Id: <20230713061208.916308-1-yanzhang.wang@intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230602070726.3807539-1-yanzhang.wang@intel.com> References: <20230602070726.3807539-1-yanzhang.wang@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Yanzhang Wang gcc/ChangeLog: * config/riscv/riscv.cc (riscv_save_reg_p): Save ra for leaf when enabling -mno-omit-leaf-frame-pointer (riscv_option_override): Override omit-frame-pointer. (riscv_frame_pointer_required): Save s0 for non-leaf function (TARGET_FRAME_POINTER_REQUIRED): Override defination * config/riscv/riscv.opt: Add option support. gcc/testsuite/ChangeLog: * gcc.target/riscv/omit-frame-pointer-1.c: New test. * gcc.target/riscv/omit-frame-pointer-2.c: New test. * gcc.target/riscv/omit-frame-pointer-3.c: New test. * gcc.target/riscv/omit-frame-pointer-4.c: New test. * gcc.target/riscv/omit-frame-pointer-test.c: New test. Signed-off-by: Yanzhang Wang --- gcc/config/riscv/riscv.cc | 34 ++++++++++++++++++- gcc/config/riscv/riscv.opt | 4 +++ .../gcc.target/riscv/omit-frame-pointer-1.c | 7 ++++ .../gcc.target/riscv/omit-frame-pointer-2.c | 7 ++++ .../gcc.target/riscv/omit-frame-pointer-3.c | 7 ++++ .../gcc.target/riscv/omit-frame-pointer-4.c | 7 ++++ .../riscv/omit-frame-pointer-test.c | 13 +++++++ 7 files changed, 78 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/omit-frame-pointer-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/omit-frame-pointer-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/omit-frame-pointer-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/omit-frame-pointer-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/omit-frame-pointer-test.c diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 706c18416db..caae6168c29 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -379,6 +379,10 @@ static const struct riscv_tune_info riscv_tune_info_table[] = { #include "riscv-cores.def" }; +/* Global variable to distinguish whether we should save and restore s0/fp for + function. */ +static bool riscv_save_frame_pointer; + void riscv_frame_info::reset(void) { total_size = 0; @@ -4948,7 +4952,11 @@ riscv_save_reg_p (unsigned int regno) if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) return true; - if (regno == RETURN_ADDR_REGNUM && crtl->calls_eh_return) + /* Need not to use ra for leaf when frame pointer is turned off by option + whatever the omit-leaf-frame's value. */ + bool keep_leaf_ra = frame_pointer_needed && crtl->is_leaf + && !TARGET_OMIT_LEAF_FRAME_POINTER; + if (regno == RETURN_ADDR_REGNUM && (crtl->calls_eh_return || keep_leaf_ra)) return true; /* If this is an interrupt handler, then must save extra registers. */ @@ -6577,6 +6585,21 @@ riscv_option_override (void) if (flag_pic) riscv_cmodel = CM_PIC; + /* We need to save the fp with ra for non-leaf functions with no fp and ra + for leaf functions while no-omit-frame-pointer with + omit-leaf-frame-pointer. The x_flag_omit_frame_pointer has the first + priority to determine whether the frame pointer is needed. If we do not + override it, the fp and ra will be stored for leaf functions, which is not + our wanted. */ + riscv_save_frame_pointer = false; + if (TARGET_OMIT_LEAF_FRAME_POINTER_P (global_options.x_target_flags)) + { + if (!global_options.x_flag_omit_frame_pointer) + riscv_save_frame_pointer = true; + + global_options.x_flag_omit_frame_pointer = 1; + } + /* We get better code with explicit relocs for CM_MEDLOW, but worse code for the others (for now). Pick the best default. */ if ((target_flags_explicit & MASK_EXPLICIT_RELOCS) == 0) @@ -7857,6 +7880,12 @@ riscv_preferred_else_value (unsigned, tree, unsigned int nops, tree *ops) return nops == 3 ? ops[2] : ops[0]; } +static bool +riscv_frame_pointer_required (void) +{ + return riscv_save_frame_pointer && !crtl->is_leaf; +} + /* Initialize the GCC target structure. */ #undef TARGET_ASM_ALIGNED_HI_OP #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" @@ -8161,6 +8190,9 @@ riscv_preferred_else_value (unsigned, tree, unsigned int nops, tree *ops) #undef TARGET_PREFERRED_ELSE_VALUE #define TARGET_PREFERRED_ELSE_VALUE riscv_preferred_else_value +#undef TARGET_FRAME_POINTER_REQUIRED +#define TARGET_FRAME_POINTER_REQUIRED riscv_frame_pointer_required + struct gcc_target targetm = TARGET_INITIALIZER; #include "gt-riscv.h" diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index dd062f1c8bd..8e6a94fd01a 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -138,6 +138,10 @@ Enable the CSR checking for the ISA-dependent CRS and the read-only CSR. The ISA-dependent CSR are only valid when the specific ISA is set. The read-only CSR can not be written by the CSR instructions. +momit-leaf-frame-pointer +Target Mask (OMIT_LEAF_FRAME_POINTER) Save +Omit the frame pointer in leaf functions. + Mask(64BIT) Mask(MUL) diff --git a/gcc/testsuite/gcc.target/riscv/omit-frame-pointer-1.c b/gcc/testsuite/gcc.target/riscv/omit-frame-pointer-1.c new file mode 100644 index 00000000000..c96123ea702 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/omit-frame-pointer-1.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64 -O2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fno-inline" } */ + +#include "omit-frame-pointer-test.c" + +/* { dg-final { scan-assembler-times "sd\tra,\[0-9\]+\\(sp\\)" 2 } } */ +/* { dg-final { scan-assembler-times "sd\ts0,\[0-9\]+\\(sp\\)" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/omit-frame-pointer-2.c b/gcc/testsuite/gcc.target/riscv/omit-frame-pointer-2.c new file mode 100644 index 00000000000..067148c6a58 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/omit-frame-pointer-2.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64 -O2 -fno-omit-frame-pointer -momit-leaf-frame-pointer -fno-inline" } */ + +#include "omit-frame-pointer-test.c" + +/* { dg-final { scan-assembler-times "sd\tra,\[0-9\]+\\(sp\\)" 1 } } */ +/* { dg-final { scan-assembler-times "sd\ts0,\[0-9\]+\\(sp\\)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/omit-frame-pointer-3.c b/gcc/testsuite/gcc.target/riscv/omit-frame-pointer-3.c new file mode 100644 index 00000000000..b4d7d6f4f0d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/omit-frame-pointer-3.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64 -O2 -fomit-frame-pointer -mno-omit-leaf-frame-pointer -fno-inline" } */ + +#include "omit-frame-pointer-test.c" + +/* { dg-final { scan-assembler-times "sd\tra,\[0-9\]+\\(sp\\)" 1 } } */ +/* { dg-final { scan-assembler-not "sd\ts0,\[0-9\]+\\(sp\\)"} } */ diff --git a/gcc/testsuite/gcc.target/riscv/omit-frame-pointer-4.c b/gcc/testsuite/gcc.target/riscv/omit-frame-pointer-4.c new file mode 100644 index 00000000000..5a5b540ef4e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/omit-frame-pointer-4.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64 -O2 -fomit-frame-pointer -momit-leaf-frame-pointer -fno-inline" } */ + +#include "omit-frame-pointer-test.c" + +/* { dg-final { scan-assembler-times "sd\tra,\[0-9\]+\\(sp\\)" 1 } } */ +/* { dg-final { scan-assembler-not "sd\ts0,\[0-9\]+\\(sp\\)"} } */ diff --git a/gcc/testsuite/gcc.target/riscv/omit-frame-pointer-test.c b/gcc/testsuite/gcc.target/riscv/omit-frame-pointer-test.c new file mode 100644 index 00000000000..cf19f001e29 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/omit-frame-pointer-test.c @@ -0,0 +1,13 @@ +int inc(int n) +{ + return n + 1; +} + + +int bar(void) +{ + int n = 100; + n = inc(n); + n = inc(n) + 100; + return n; +} -- 2.40.1