From: chenyixuan@iscas.ac.cn
To: gcc-patches@gcc.gnu.org
Cc: kito.cheng@gmail.com, andrew@sifive.com, shiyulong@iscas.ac.cn,
oriachiuan@gmail.com, shihua@iscas.ac.cn, jiawei@iscas.ac.cn,
XYenChi <chenyixuan@iscas.ac.cn>
Subject: [PATCH] Add VXRM enum
Date: Thu, 13 Jul 2023 14:31:42 +0800 [thread overview]
Message-ID: <20230713063142.66310-1-chenyixuan@iscas.ac.cn> (raw)
From: XYenChi <chenyixuan@iscas.ac.cn>
Noticed that the rvv-intrinsic-doc updated the __RISCV_VXRM.
gcc/ChangeLog:Add __RISCV_VXRM enum to riscv_vector.h
2023-07-13 XYenChi <chenyixuan@iscas.ac.cn>
* config/riscv/riscv_vector.h (enum __RISCV_VXRM):Add an enum __RISCV_VXRM to help express the rounding modes.
---
gcc/config/riscv/riscv_vector.h | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/gcc/config/riscv/riscv_vector.h b/gcc/config/riscv/riscv_vector.h
index ff54b6be863..0a90816be1a 100644
--- a/gcc/config/riscv/riscv_vector.h
+++ b/gcc/config/riscv/riscv_vector.h
@@ -42,6 +42,13 @@ enum RVV_CSR {
RVV_VCSR,
};
+enum __RISCV_VXRM {
+ __RISCV_VXRM_RNU = 0,
+ __RISCV_VXRM_RNE = 1,
+ __RISCV_VXRM_RDN = 2,
+ __RISCV_VXRM_ROD = 3,
+};
+
__extension__ extern __inline unsigned long
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vread_csr(enum RVV_CSR csr)
--
2.41.0
next reply other threads:[~2023-07-13 6:32 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-13 6:31 chenyixuan [this message]
2023-07-13 6:54 ` Robin Dapp
2023-07-13 7:24 ` Kito Cheng
2023-07-13 7:54 ` 陈逸轩
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