From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oi1-x230.google.com (mail-oi1-x230.google.com [IPv6:2607:f8b0:4864:20::230]) by sourceware.org (Postfix) with ESMTPS id EC3783858439 for ; Thu, 13 Jul 2023 10:22:33 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org EC3783858439 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linaro.org Received: by mail-oi1-x230.google.com with SMTP id 5614622812f47-3a1ebb85f99so546292b6e.2 for ; Thu, 13 Jul 2023 03:22:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689243753; x=1691835753; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HwtaEEMZe3SnTp9inMCk6AQlAVG8/PwROwShhgmC5YM=; b=eb9DObSHOAkHdErX+KfeZ/pYh9GHhVgN+1+Ug8NBqfrRjHKVVptptikqdQtsl6EUoi 11pPbxLD1Ul/yJf8J7uUa4FP1jz98vq4LKH1UuAp8+kE4hrHjnE7LD14cqqJz6IRA1Ww SAFK6CO/pWYwe4V3ghLRlqByIZ0eVMVoZnifahrlU28xVxKJ11/QA5lzQTQy/1lbw5Vh 1hm8QswyWCNhjvg7yObv2sJFyk+dWZkqhQQjIyJXew7mgJE5jaXTX7a5B6KGYThB8uCI kkVqvc918Juw5HncpaTe4DQsRcW3iIRywUR9aUIuEBAEAFL8+JaST8RM0bfXkBPangkq CnNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689243753; x=1691835753; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HwtaEEMZe3SnTp9inMCk6AQlAVG8/PwROwShhgmC5YM=; b=AXolO5OAHIWQBklMLPF7+3r9bKBFC9+R9AVs0VcwggimhNKfyZaw6WRMPAMOSpmyDG ek8ESwrfP8rjF9o8HH+TSK0aUAbUlJAV1dRRCqsoHCEG9Q3zIxkyMJ8S7AXulVLeTe/I /sevxhrCZ6nk/qBMiInR12vw+xEe8ZQ6NWU5/Ch2c0uJejoZIdPjKpfhX4Mx3cWoAg0B fTNJvSJEPG6vPCliv2GdVpjSbdp/F7sB8asBb1Taucu6KTO6YG06jRxXkYOUC19r+VBU KEiE5fQrfX2/DA7RHFDLqY4mcpXosx+DNDUl1bX0aRuMwTL2Q6FEm4pXUzTxwfsTjUZ4 FPdQ== X-Gm-Message-State: ABy/qLaIIoOIqoIDrZH0EKjBnj0wT5gcAygf0FdpOAwa6hIdkx8PFyrw WEIbcH70q+6O5tJNAlBXJOPqM/1MTdGdcdMUwfMnYojw X-Google-Smtp-Source: APBJJlHXD0hjPKMkoB8fUGN01iOwPVJrq3WTeqsGBRLS+Y7FL2r7bSM7FNe0/ohKXsATO+bnx2rqpQ== X-Received: by 2002:a05:6808:1645:b0:3a3:61df:da with SMTP id az5-20020a056808164500b003a361df00damr1471415oib.53.1689243752956; Thu, 13 Jul 2023 03:22:32 -0700 (PDT) Received: from localhost.localdomain ([139.178.84.207]) by smtp.gmail.com with ESMTPSA id a9-20020a05680802c900b003a020d24d7dsm2707263oid.56.2023.07.13.03.22.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Jul 2023 03:22:32 -0700 (PDT) From: Christophe Lyon To: gcc-patches@gcc.gnu.org, Kyrylo.Tkachov@arm.com, richard.earnshaw@arm.com, richard.sandiford@arm.com Cc: Christophe Lyon Subject: [PATCH 5/6] arm: [MVE intrinsics] factorize vcmlaq Date: Thu, 13 Jul 2023 10:22:23 +0000 Message-Id: <20230713102224.1161596-5-christophe.lyon@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230713102224.1161596-1-christophe.lyon@linaro.org> References: <20230713102224.1161596-1-christophe.lyon@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Factorize vcmlaq builtins so that they use parameterized names. 2023-17-13 Christophe Lyon gcc/ * config/arm/arm_mve_builtins.def (vcmlaq_rot90_f) (vcmlaq_rot270_f, vcmlaq_rot180_f, vcmlaq_f): Add "_f" suffix. * config/arm/iterators.md (MVE_VCMLAQ_M): New. (mve_insn): Add vcmla. (rot): Add VCMLAQ_M_F, VCMLAQ_ROT90_M_F, VCMLAQ_ROT180_M_F, VCMLAQ_ROT270_M_F. (mve_rot): Add VCMLAQ_M_F, VCMLAQ_ROT90_M_F, VCMLAQ_ROT180_M_F, VCMLAQ_ROT270_M_F. * config/arm/mve.md (mve_vcmlaq): Rename into ... (@mve_q_f): ... this. (mve_vcmlaq_m_f, mve_vcmlaq_rot180_m_f) (mve_vcmlaq_rot270_m_f, mve_vcmlaq_rot90_m_f): Merge into ... (@mve_q_m_f): ... this. --- gcc/config/arm/arm_mve_builtins.def | 10 ++--- gcc/config/arm/iterators.md | 19 ++++++++- gcc/config/arm/mve.md | 64 ++++------------------------- 3 files changed, 29 insertions(+), 64 deletions(-) diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def index 56358c0bd02..43dacc3dda1 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -378,6 +378,10 @@ VAR3 (TERNOP_NONE_NONE_NONE_NONE, vmlasq_n_s, v16qi, v8hi, v4si) VAR3 (TERNOP_NONE_NONE_NONE_NONE, vmlaq_n_s, v16qi, v8hi, v4si) VAR3 (TERNOP_NONE_NONE_NONE_NONE, vmladavaxq_s, v16qi, v8hi, v4si) VAR3 (TERNOP_NONE_NONE_NONE_NONE, vmladavaq_s, v16qi, v8hi, v4si) +VAR2 (TERNOP_NONE_NONE_NONE_NONE, vcmlaq_rot90_f, v8hf, v4sf) +VAR2 (TERNOP_NONE_NONE_NONE_NONE, vcmlaq_rot270_f, v8hf, v4sf) +VAR2 (TERNOP_NONE_NONE_NONE_NONE, vcmlaq_rot180_f, v8hf, v4sf) +VAR2 (TERNOP_NONE_NONE_NONE_NONE, vcmlaq_f, v8hf, v4sf) VAR3 (TERNOP_NONE_NONE_NONE_IMM, vsriq_n_s, v16qi, v8hi, v4si) VAR3 (TERNOP_NONE_NONE_NONE_IMM, vsliq_n_s, v16qi, v8hi, v4si) VAR2 (TERNOP_UNONE_UNONE_UNONE_PRED, vrev32q_m_u, v16qi, v8hi) @@ -876,9 +880,3 @@ VAR3 (QUADOP_NONE_NONE_UNONE_IMM_PRED, vshlcq_m_vec_s, v16qi, v8hi, v4si) VAR3 (QUADOP_NONE_NONE_UNONE_IMM_PRED, vshlcq_m_carry_s, v16qi, v8hi, v4si) VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vshlcq_m_vec_u, v16qi, v8hi, v4si) VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vshlcq_m_carry_u, v16qi, v8hi, v4si) - -/* optabs without any suffixes. */ -VAR2 (TERNOP_NONE_NONE_NONE_NONE, vcmlaq_rot90, v8hf, v4sf) -VAR2 (TERNOP_NONE_NONE_NONE_NONE, vcmlaq_rot270, v8hf, v4sf) -VAR2 (TERNOP_NONE_NONE_NONE_NONE, vcmlaq_rot180, v8hf, v4sf) -VAR2 (TERNOP_NONE_NONE_NONE_NONE, vcmlaq, v8hf, v4sf) diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index 9f71404e26c..b13ff53d36f 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -911,6 +911,10 @@ VCMULQ_M_F VCMULQ_ROT90_M_F VCMULQ_ROT180_M_F VCMULQ_ROT270_M_F ]) +(define_int_iterator MVE_VCMLAQ_M [ + VCMLAQ_M_F VCMLAQ_ROT90_M_F VCMLAQ_ROT180_M_F VCMLAQ_ROT270_M_F + ]) + (define_int_attr mve_insn [ (UNSPEC_VCADD90 "vcadd") (UNSPEC_VCADD270 "vcadd") (UNSPEC_VCMUL "vcmul") (UNSPEC_VCMUL90 "vcmul") (UNSPEC_VCMUL180 "vcmul") (UNSPEC_VCMUL270 "vcmul") @@ -942,6 +946,7 @@ (VCLSQ_M_S "vcls") (VCLSQ_S "vcls") (VCLZQ_M_S "vclz") (VCLZQ_M_U "vclz") + (VCMLAQ_M_F "vcmla") (VCMLAQ_ROT90_M_F "vcmla") (VCMLAQ_ROT180_M_F "vcmla") (VCMLAQ_ROT270_M_F "vcmla") (VCMULQ_M_F "vcmul") (VCMULQ_ROT90_M_F "vcmul") (VCMULQ_ROT180_M_F "vcmul") (VCMULQ_ROT270_M_F "vcmul") (VCREATEQ_S "vcreate") (VCREATEQ_U "vcreate") (VCREATEQ_F "vcreate") (VDUPQ_M_N_S "vdup") (VDUPQ_M_N_U "vdup") (VDUPQ_M_N_F "vdup") @@ -1204,6 +1209,7 @@ (VSUBQ_M_N_S "vsub") (VSUBQ_M_N_U "vsub") (VSUBQ_M_N_F "vsub") (VSUBQ_M_S "vsub") (VSUBQ_M_U "vsub") (VSUBQ_M_F "vsub") (VSUBQ_N_S "vsub") (VSUBQ_N_U "vsub") (VSUBQ_N_F "vsub") + (UNSPEC_VCMLA "vcmla") (UNSPEC_VCMLA90 "vcmla") (UNSPEC_VCMLA180 "vcmla") (UNSPEC_VCMLA270 "vcmla") ]) (define_int_attr isu [ @@ -2198,7 +2204,12 @@ (VCMULQ_M_F "0") (VCMULQ_ROT90_M_F "90") (VCMULQ_ROT180_M_F "180") - (VCMULQ_ROT270_M_F "270")]) + (VCMULQ_ROT270_M_F "270") + (VCMLAQ_M_F "0") + (VCMLAQ_ROT90_M_F "90") + (VCMLAQ_ROT180_M_F "180") + (VCMLAQ_ROT270_M_F "270") + ]) ;; The complex operations when performed on a real complex number require two ;; instructions to perform the operation. e.g. complex multiplication requires @@ -2250,7 +2261,11 @@ (VCMULQ_M_F "") (VCMULQ_ROT90_M_F "_rot90") (VCMULQ_ROT180_M_F "_rot180") - (VCMULQ_ROT270_M_F "_rot270")]) + (VCMULQ_ROT270_M_F "_rot270") + (VCMLAQ_M_F "") + (VCMLAQ_ROT90_M_F "_rot90") + (VCMLAQ_ROT180_M_F "_rot180") + (VCMLAQ_ROT270_M_F "_rot270")]) (define_int_attr fcmac1 [(UNSPEC_VCMLA "a") (UNSPEC_VCMLA_CONJ "a") (UNSPEC_VCMLA180 "s") (UNSPEC_VCMLA180_CONJ "s")]) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 0b99bf017dc..a2cbcff1a6f 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -2087,7 +2087,7 @@ ;; ;; [vcmlaq, vcmlaq_rot90, vcmlaq_rot180, vcmlaq_rot270]) ;; -(define_insn "mve_vcmlaq" +(define_insn "@mve_q_f" [ (set (match_operand:MVE_0 0 "s_register_operand" "=w,w") (plus:MVE_0 (match_operand:MVE_0 1 "reg_or_zero_operand" "Dz,0") @@ -3180,70 +3180,22 @@ (set_attr "length""8")]) ;; -;; [vcmlaq_m_f]) -;; -(define_insn "mve_vcmlaq_m_f" - [ - (set (match_operand:MVE_0 0 "s_register_operand" "=w") - (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") - (match_operand:MVE_0 2 "s_register_operand" "w") - (match_operand:MVE_0 3 "s_register_operand" "w") - (match_operand: 4 "vpr_register_operand" "Up")] - VCMLAQ_M_F)) - ] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vpst\;vcmlat.f%# %q0, %q2, %q3, #0" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - -;; -;; [vcmlaq_rot180_m_f]) -;; -(define_insn "mve_vcmlaq_rot180_m_f" - [ - (set (match_operand:MVE_0 0 "s_register_operand" "=w") - (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") - (match_operand:MVE_0 2 "s_register_operand" "w") - (match_operand:MVE_0 3 "s_register_operand" "w") - (match_operand: 4 "vpr_register_operand" "Up")] - VCMLAQ_ROT180_M_F)) - ] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vpst\;vcmlat.f%# %q0, %q2, %q3, #180" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - -;; -;; [vcmlaq_rot270_m_f]) +;; [vcmlaq_m_f] +;; [vcmlaq_rot90_m_f] +;; [vcmlaq_rot180_m_f] +;; [vcmlaq_rot270_m_f] ;; -(define_insn "mve_vcmlaq_rot270_m_f" - [ - (set (match_operand:MVE_0 0 "s_register_operand" "=w") - (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") - (match_operand:MVE_0 2 "s_register_operand" "w") - (match_operand:MVE_0 3 "s_register_operand" "w") - (match_operand: 4 "vpr_register_operand" "Up")] - VCMLAQ_ROT270_M_F)) - ] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vpst\;vcmlat.f%# %q0, %q2, %q3, #270" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - -;; -;; [vcmlaq_rot90_m_f]) -;; -(define_insn "mve_vcmlaq_rot90_m_f" +(define_insn "@mve_q_m_f" [ (set (match_operand:MVE_0 0 "s_register_operand" "=w") (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") (match_operand:MVE_0 3 "s_register_operand" "w") (match_operand: 4 "vpr_register_operand" "Up")] - VCMLAQ_ROT90_M_F)) + MVE_VCMLAQ_M)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vpst\;vcmlat.f%# %q0, %q2, %q3, #90" + "vpst\;t.f%#\t%q0, %q2, %q3, #" [(set_attr "type" "mve_move") (set_attr "length""8")]) -- 2.34.1