From: Die Li <lidie@eswincomputing.com>
To: gcc-patches@gcc.gnu.org
Cc: kito.cheng@gmail.com, palmer@dabbelt.com, jeffeyalaw@gmail.com,
lidie@eswincomputing.com
Subject: [PATCH] RISC-V: Remove the redundant expressions in the and<mode>3.
Date: Fri, 14 Jul 2023 02:02:05 +0000 [thread overview]
Message-ID: <20230714020205.16214-1-lidie@eswincomputing.com> (raw)
When generating the gen_and<mode>3 function based on the and<mode>3
template, it produces the expression emit_insn (gen_rtx_SET (operand0,
gen_rtx_AND (<mode>, operand1, operand2)));, which is identical to the
portion I removed in this patch. Therefore, the redundant portion can be
deleted.
Signed-off-by: Die Li <lidie@eswincomputing.com>
gcc/ChangeLog:
* config/riscv/riscv.md: Remove redundant portion in and<mode>3.
---
gcc/config/riscv/riscv.md | 5 -----
1 file changed, 5 deletions(-)
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 7988026d129..c4f8eb9488e 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -1491,11 +1491,6 @@
DONE;
}
}
- else
- {
- emit_move_insn (operands[0], gen_rtx_AND (<MODE>mode, operands[1], operands[2]));
- DONE;
- }
})
(define_insn "*and<mode>3"
--
2.17.1
next reply other threads:[~2023-07-14 2:02 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-14 2:02 Die Li [this message]
2023-07-14 2:34 ` Palmer Dabbelt
2023-07-14 2:41 ` Kito Cheng
2023-07-14 2:44 ` Palmer Dabbelt
2023-07-14 2:50 ` Jeff Law
2023-07-14 2:52 ` Jeff Law
2023-07-14 12:32 ` Kito Cheng
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