From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by sourceware.org (Postfix) with ESMTPS id EBC803858CD1 for ; Fri, 14 Jul 2023 13:21:02 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org EBC803858CD1 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1689340863; x=1720876863; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=sgaP2IBaCNM7ee+EIhE6hnre5KD3WR6IJ23dQTvPC+Q=; b=TuSBNYUb6jGN0F9SzAab8i2FgjTfgD75ShxwWQg7izHzEf/HI691rn4+ 0LTGZoLUIVoJ2EBiwTGhxmaMcNleAoP9eizo60lYPnme7U0SUJAnD2U67 6E4YEPhSyySNipHYHIJWE5zwhD+o1SGIjszhneTQiH9FnIiRkp7NBnfKd TA7Mv+F2/ZP7FdHwQcKa264vgagAXhK78jdje2OzgB21M8mcpU+8CPKoN JvhDaz76VCeU+qIWUSK7VK4DLZ2IuKwq4RhYBpuTsgFtix5TeaXfJndGu VPhJ2onmST4+HKWdpgvvEhs5rWj/yOJBH34l1QoQbkc1yTXDCySNb84rP g==; X-IronPort-AV: E=McAfee;i="6600,9927,10770"; a="362939757" X-IronPort-AV: E=Sophos;i="6.01,205,1684825200"; d="scan'208";a="362939757" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jul 2023 06:20:55 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10770"; a="846455682" X-IronPort-AV: E=Sophos;i="6.01,205,1684825200"; d="scan'208";a="846455682" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga004.jf.intel.com with ESMTP; 14 Jul 2023 06:20:52 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id C21881005692; Fri, 14 Jul 2023 21:20:51 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Fix RVV frm run test failure on RV32 Date: Fri, 14 Jul 2023 21:20:50 +0800 Message-Id: <20230714132050.2728477-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-10.8 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_NUMSUBJECT,KAM_SHORT,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Pan Li Refine the run test case to avoid interactive checking in RV32, by separating each checks in different functions. Signed-off-by: Pan Li gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-frm-run-1.c: Fix failure on RV32. --- .../riscv/rvv/base/float-point-frm-run-1.c | 58 ++++++++++--------- 1 file changed, 31 insertions(+), 27 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c index 210c49c5e8d..1d90b4f50d9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c @@ -5,6 +5,24 @@ #include #include +#define DEFINE_TEST_FRM_FUNC(FRM) \ +vfloat32m1_t __attribute__ ((noinline)) \ +test_float_point_frm_run_##FRM (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) \ +{ \ + vfloat32m1_t result; \ + \ + set_frm (0); \ + \ + result = __riscv_vfadd_vv_f32m1_rm (op1, result, FRM, vl); \ + \ + assert_equal (FRM, get_frm (), "The value of frm should be " #FRM "."); \ + \ + return result; \ +} + +#define CALL_TEST_FUNC(FRM, op1, op2, vl) \ + test_float_point_frm_run_##FRM (op1, op2, vl) + static int get_frm () { @@ -31,40 +49,22 @@ set_frm (int frm) ); } -static inline void +void __attribute__ ((noinline)) \ assert_equal (int a, int b, char *message) { if (a != b) { - printf (message); + fprintf (stdout, message); + fflush (stdout); __builtin_abort (); } } -vfloat32m1_t __attribute__ ((noinline)) -test_float_point_frm_run (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) -{ - set_frm (0); - - vfloat32m1_t result; - - result = __riscv_vfadd_vv_f32m1_rm (op1, result, 1, vl); - assert_equal (1, get_frm (), "The value of frm register should be 1."); - - result = __riscv_vfadd_vv_f32m1_rm (op1, result, 2, vl); - assert_equal (2, get_frm (), "The value of frm register should be 2."); - - result = __riscv_vfadd_vv_f32m1_rm (op1, result, 3, vl); - assert_equal (3, get_frm (), "The value of frm register should be 3."); - - result = __riscv_vfadd_vv_f32m1_rm (op1, result, 4, vl); - assert_equal (4, get_frm (), "The value of frm register should be 4."); - - result = __riscv_vfadd_vv_f32m1_rm (op1, result, 0, vl); - assert_equal (0, get_frm (), "The value of frm register should be 0."); - - return result; -} +DEFINE_TEST_FRM_FUNC (0) +DEFINE_TEST_FRM_FUNC (1) +DEFINE_TEST_FRM_FUNC (2) +DEFINE_TEST_FRM_FUNC (3) +DEFINE_TEST_FRM_FUNC (4) int main () @@ -73,7 +73,11 @@ main () vfloat32m1_t op1; vfloat32m1_t op2; - test_float_point_frm_run (op1, op2, vl); + CALL_TEST_FUNC (0, op1, op2, vl); + CALL_TEST_FUNC (1, op1, op2, vl); + CALL_TEST_FUNC (2, op1, op2, vl); + CALL_TEST_FUNC (3, op1, op2, vl); + CALL_TEST_FUNC (4, op1, op2, vl); return 0; } -- 2.34.1