From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by sourceware.org (Postfix) with ESMTPS id B276C3858D1E for ; Mon, 17 Jul 2023 03:33:38 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B276C3858D1E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1689564818; x=1721100818; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=CkBM550u1hpaN1Eh0JMZeBT3ZPyN9g1jM9Nxbfpy3b0=; b=MhUnYJChZMQb3pICY5ktI9oHw97owyZ0MGThM/RlNxUdP+C3H6OrPGX0 A0puMHcuru03yaV0R8xM6+TjAJ+J270SD0+Uz2SMektUDAv/z8L9heVwp q1j8QPwIoOroJwAqxX4JtCJcIYH+t8wyAlu13qCHwTybdlol8GbS0yf1w S8w57tAO8yeFUomIGXrS/s7kmpz2sGUUTSEE/61/OQjXguYKL3Aswzb0s lq/l1ELQA0Aw8vmirXaNcZNJ++MkidP+6NTJv1jUcIpjw//ZCRzlavJKi tDwdyk1zH69HMPg+LTm4hJdouMObxElOXlI+yBSxfg5NxSc2x8H25yGAJ w==; X-IronPort-AV: E=McAfee;i="6600,9927,10773"; a="369386743" X-IronPort-AV: E=Sophos;i="6.01,211,1684825200"; d="scan'208";a="369386743" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jul 2023 20:33:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10773"; a="726377552" X-IronPort-AV: E=Sophos;i="6.01,211,1684825200"; d="scan'208";a="726377552" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga007.fm.intel.com with ESMTP; 16 Jul 2023 20:33:35 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id BA1EB1005170; Mon, 17 Jul 2023 11:33:34 +0800 (CST) From: Haochen Jiang To: gcc-patches@gcc.gnu.org Cc: hongtao.liu@intel.com, ubizjak@gmail.com Subject: [PATCH] [gcc-wwwdocs]gcc-13/14: Mention Intel new ISA and march support Date: Mon, 17 Jul 2023 11:33:34 +0800 Message-Id: <20230717033334.2376251-1-haochen.jiang@intel.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-10.8 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi all, This patch adds documentation to wwwdocs to mention the recent introduction of Intel new ISA and march. Ok for trunk? BRs, Haochen --- htdocs/gcc-13/changes.html | 4 ++++ htdocs/gcc-14/changes.html | 34 +++++++++++++++++++++++++++++++++- 2 files changed, 37 insertions(+), 1 deletion(-) diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html index 39414e18..68e8c5cc 100644 --- a/htdocs/gcc-13/changes.html +++ b/htdocs/gcc-13/changes.html @@ -593,6 +593,10 @@ You may also want to check out our
  • GCC now supports the Intel CPU named Granite Rapids through -march=graniterapids. + The switch enables the AMX-FP16, PREFETCHI ISA extensions. +
    • +
  • GCC now supports the Intel CPU named Granite Rapids D through + -march=graniterapids-d. The switch enables the AMX-FP16, PREFETCHI and AMX-COMPLEX ISA extensions.
  • GCC now supports AMD CPUs based on the znver4 core diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html index 3f797642..dad1ba53 100644 --- a/htdocs/gcc-14/changes.html +++ b/htdocs/gcc-14/changes.html @@ -108,7 +108,39 @@ a work-in-progress.

    - +

    IA-32/x86-64

    +
      +
    • New ISA extension support for Intel AVX-VNNI-INT16 was added. + AVX-VNNI-INT16 intrinsics are available via the -mavxvnniint16 + compiler switch. +
      • +
    • New ISA extension support for Intel SHA512 was added. + SHA512 intrinsics are available via the -msha512 + compiler switch. +
      • +
    • New ISA extension support for Intel SM3 was added. + SM3 intrinsics are available via the -msm3 + compiler switch. +
      • +
    • New ISA extension support for Intel SM4 was added. + SM4 intrinsics are available via the -msm4 + compiler switch. +
      • +
    • GCC now supports the Intel CPU named Arrow Lake through + -march=arrowlake. + Based on Alder Lake, the switch further enables the AVX-IFMA, + AVX-VNNI-INT8, AVX-NE-CONVERT and CMPccXADD ISA extensions. +
      • +
    • GCC now supports the Intel CPU named Arrow Lake S through + -march=arrowlake-s. + Based on Arrow Lake, the switch further enables the AVX-VNNI-INT16, SHA512, + SM3 and SM4 ISA extensions. +
      • +
    • GCC now supports the Intel CPU named Lunar Lake through + -march=lunarlake. + Lunar Lake is based on Arrow Lake S. +
      • +
    -- 2.31.1