From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
To: gcc-patches@gcc.gnu.org
Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, palmer@dabbelt.com,
palmer@rivosinc.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com,
Juzhe-Zhong <juzhe.zhong@rivai.ai>
Subject: [PATCH] RISC-V: Add TARGET_MIN_VLEN > 4096 check
Date: Mon, 17 Jul 2023 14:04:23 +0800 [thread overview]
Message-ID: <20230717060423.31423-1-juzhe.zhong@rivai.ai> (raw)
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_option_override): Report ERROR for TARGET_MIN_VLEN > 4096
---
gcc/config/riscv/riscv.cc | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 6ed735d6983..ce523eea9ba 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -6672,6 +6672,14 @@ riscv_option_override (void)
riscv_stack_protector_guard_offset = offs;
}
+ /* FIXME: We don't allow TARGET_MIN_VLEN > 4096 since the datatypes of
+ both GET_MODE_SIZE and GET_MODE_BITSIZE are poly_uint16.
+
+ We can only allow TARGET_MIN_VLEN * 8 (LMUL) < 65535. */
+ if (TARGET_MIN_VLEN > 4096)
+ error (
+ "Current RISC-V GCC can not support VLEN > 4096bit for 'V' Extension");
+
/* Convert -march to a chunks count. */
riscv_vector_chunks = riscv_convert_vector_bits ();
}
--
2.36.1
next reply other threads:[~2023-07-17 6:04 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-17 6:04 Juzhe-Zhong [this message]
2023-07-17 6:12 ` Kito Cheng
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