From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtpbg151.qq.com (smtpbg151.qq.com [18.169.211.239]) by sourceware.org (Postfix) with ESMTPS id B998C3858D28 for ; Mon, 17 Jul 2023 14:20:12 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B998C3858D28 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp81t1689603606td1k344x Received: from server1.localdomain ( [58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 17 Jul 2023 22:20:05 +0800 (CST) X-QQ-SSF: 01400000000000G0T000000A0000000 X-QQ-FEAT: PS/N6jJLnDZTesopcX1dg9uLoZZ8y3vEjzFJ9sQz5j+8yeShGIxn9hI5re86j MbT2xAjbiD7i6tQTbrFKmnP2dph9BeKGsf4PLtQgHnpLeGQCWRVkmUxadwXBwHArzVketJB h+FhQVoWUpOsP5pN9BSq7K9HdcO8TtsVxu5yoGWwbED+tBaDecLv48nu/U/QzQNyZQvvOh8 TcsVGgfJdKpVMK5IU1NanrVtdpv5BSQAy1nHZs+pioOuQ9GWr95t9RNGueQcnh7l6R+9IpH jQQV0kToioU9dL4V9QAJv/H5wdQDXTboHD9y4Mk937edUK4keqPBe1/SZSaRdhAyNo2UWIP H1TKuniqTkw54o3JP+McmuQrx4twXLGWkAzNOq+GJfXkDTqm/NLpHlSM/r9J7zE2l1pY11w pN2QIW+lptg= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 11691211917986755279 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: kito.cheng@sifive.com, palmer@rivosinc.com, rdapp.gcc@gmail.com, jeffreyalaw@gmail.com, kito.cheng@gmail.com, Juzhe-Zhong Subject: [PATCH V3] RISC-V: Add TARGET_MIN_VLEN > 4096 check Date: Mon, 17 Jul 2023 22:20:02 +0800 Message-Id: <20230717142002.295213-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_SHORT,RCVD_IN_BARRACUDACENTRAL,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: gcc/ChangeLog: * config/riscv/riscv.cc (riscv_option_override): Add sorry check. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/zvl-unimplemented-1.c: New test. * gcc.target/riscv/rvv/base/zvl-unimplemented-2.c: New test. --- gcc/config/riscv/riscv.cc | 8 ++++++++ .../gcc.target/riscv/rvv/base/zvl-unimplemented-1.c | 4 ++++ .../gcc.target/riscv/rvv/base/zvl-unimplemented-2.c | 4 ++++ 3 files changed, 16 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-2.c diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 6ed735d6983..82e7c27b057 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -6672,6 +6672,14 @@ riscv_option_override (void) riscv_stack_protector_guard_offset = offs; } + /* FIXME: We don't allow TARGET_MIN_VLEN > 4096 since the datatypes of + both GET_MODE_SIZE and GET_MODE_BITSIZE are poly_uint16. + + We can only allow TARGET_MIN_VLEN * 8 (LMUL) < 65535. */ + if (TARGET_MIN_VLEN > 4096) + sorry ( + "Current RISC-V GCC can not support VLEN > 4096bit for 'V' Extension"); + /* Convert -march to a chunks count. */ riscv_vector_chunks = riscv_convert_vector_bits (); } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-1.c new file mode 100644 index 00000000000..03f67035ca4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-1.c @@ -0,0 +1,4 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv_zvl8192b -mabi=lp64d --param riscv-autovec-preference=fixed-vlmax" } */ + +void foo () {} // { dg-excess-errors "sorry, unimplemented: Current RISC-V GCC can not support VLEN > 4096bit for 'V' Extension" } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-2.c new file mode 100644 index 00000000000..075112f2f81 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-2.c @@ -0,0 +1,4 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv_zvl8192b -mabi=lp64d --param riscv-autovec-preference=scalable" } */ + +void foo () {} // { dg-excess-errors "sorry, unimplemented: Current RISC-V GCC can not support VLEN > 4096bit for 'V' Extension" } -- 2.36.1