From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id 44F6A38582A1 for ; Tue, 18 Jul 2023 11:07:02 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 44F6A38582A1 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.20.4.45]) by gateway (Coremail) with SMTP id _____8Cx5_FScrZkHrUGAA--.17558S3; Tue, 18 Jul 2023 19:06:58 +0800 (CST) Received: from loongson-pc.loongson.cn (unknown [10.20.4.45]) by localhost.localdomain (Coremail) with SMTP id AQAAf8CxriNFcrZkjiwzAA--.35305S5; Tue, 18 Jul 2023 19:06:57 +0800 (CST) From: Chenghui Pan To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, i@xen0n.name, chenglulu@loongson.cn, xuchenghua@loongson.cn Subject: [PATCH v2 1/8] LoongArch: Added Loongson SX vector directive compilation framework. Date: Tue, 18 Jul 2023 19:06:18 +0800 Message-Id: <20230718110625.88834-2-panchenghui@loongson.cn> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230718110625.88834-1-panchenghui@loongson.cn> References: <20230718110625.88834-1-panchenghui@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CM-TRANSID:AQAAf8CxriNFcrZkjiwzAA--.35305S5 X-CM-SenderInfo: psdquxxhqjx33l6o00pqjv00gofq/1tbiAQAQBGS2ES4EEwAAsv X-Coremail-Antispam: 1Uk129KBj9fXoW3uw1rGF43XFyDWFWrZrWrJFc_yoW8GF1rCo WFyF98Zw18Gr4S934DtwnIqrWDtr1jyr4UA397Zw4UGFs7JFy5JFyUWr1Yvry7Ja97Wr98 A34UW397Ja4xJrnxl-sFpf9Il3svdjkaLaAFLSUrUUUUUb8apTn2vfkv8UJUUUU8wcxFpf 9Il3svdxBIdaVrn0xqx4xG64xvF2IEw4CE5I8CrVC2j2Jv73VFW2AGmfu7bjvjm3AaLaJ3 UjIYCTnIWjp_UUUY17kC6x804xWl14x267AKxVWUJVW8JwAFc2x0x2IEx4CE42xK8VAvwI 8IcIk0rVWrJVCq3wAFIxvE14AKwVWUXVWUAwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xG Y2AK021l84ACjcxK6xIIjxv20xvE14v26r1j6r1xM28EF7xvwVC0I7IYx2IY6xkF7I0E14 v26r1j6r4UM28EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAF wI0_Gr1j6F4UJwAS0I0E0xvYzxvE52x082IY62kv0487Mc804VCY07AIYIkI8VC2zVCFFI 0UMc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2IY67AKxVWUXVWUAwAv7VC2z280 aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0Y48IcxkI7VAKI48JMxAIw28Icx kI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2Iq xVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwIxGrwCI42 IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8JwCI42IY 6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aV CY1x0267AKxVWUJVW8JbIYCTnIWIevJa73UjIFyTuYvjxU7_MaUUUUU X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Lulu Cheng gcc/ChangeLog: * config/loongarch/genopts/loongarch-strings: Added compilation framework. * config/loongarch/genopts/loongarch.opt.in: Ditto. * config/loongarch/loongarch-c.cc (loongarch_cpu_cpp_builtins): Ditto. * config/loongarch/loongarch-def.c: Ditto. * config/loongarch/loongarch-def.h (N_ISA_EXT_TYPES): Ditto. (ISA_EXT_SIMD_LSX): Ditto. (N_SWITCH_TYPES): Ditto. (SW_LSX): Ditto. (struct loongarch_isa): Ditto. * config/loongarch/loongarch-driver.cc (APPEND_SWITCH): Ditto. (driver_get_normalized_m_opts): Ditto. * config/loongarch/loongarch-driver.h (driver_get_normalized_m_opts): Ditto. * config/loongarch/loongarch-opts.cc (loongarch_config_target): Ditto. (isa_str): Ditto. * config/loongarch/loongarch-opts.h (ISA_HAS_LSX): Ditto. * config/loongarch/loongarch-str.h (OPTSTR_LSX): Ditto. * config/loongarch/loongarch.opt: Ditto. --- .../loongarch/genopts/loongarch-strings | 3 + gcc/config/loongarch/genopts/loongarch.opt.in | 8 +- gcc/config/loongarch/loongarch-c.cc | 7 ++ gcc/config/loongarch/loongarch-def.c | 4 + gcc/config/loongarch/loongarch-def.h | 7 +- gcc/config/loongarch/loongarch-driver.cc | 10 +++ gcc/config/loongarch/loongarch-driver.h | 1 + gcc/config/loongarch/loongarch-opts.cc | 82 ++++++++++++++++++- gcc/config/loongarch/loongarch-opts.h | 1 + gcc/config/loongarch/loongarch-str.h | 2 + gcc/config/loongarch/loongarch.opt | 8 +- 11 files changed, 128 insertions(+), 5 deletions(-) diff --git a/gcc/config/loongarch/genopts/loongarch-strings b/gcc/config/loongarch/genopts/loongarch-strings index a40998ead97..24a5025061f 100644 --- a/gcc/config/loongarch/genopts/loongarch-strings +++ b/gcc/config/loongarch/genopts/loongarch-strings @@ -40,6 +40,9 @@ OPTSTR_SOFT_FLOAT soft-float OPTSTR_SINGLE_FLOAT single-float OPTSTR_DOUBLE_FLOAT double-float +# SIMD extensions +OPTSTR_LSX lsx + # -mabi= OPTSTR_ABI_BASE abi STR_ABI_BASE_LP64D lp64d diff --git a/gcc/config/loongarch/genopts/loongarch.opt.in b/gcc/config/loongarch/genopts/loongarch.opt.in index 4b9b4ac273e..338d77a7e40 100644 --- a/gcc/config/loongarch/genopts/loongarch.opt.in +++ b/gcc/config/loongarch/genopts/loongarch.opt.in @@ -76,6 +76,9 @@ m@@OPTSTR_DOUBLE_FLOAT@@ Target Driver RejectNegative Var(la_opt_switches) Mask(FORCE_F64) Negative(m@@OPTSTR_SOFT_FLOAT@@) Allow hardware floating-point instructions to cover both 32-bit and 64-bit operations. +m@@OPTSTR_LSX@@ +Target RejectNegative Var(la_opt_switches) Mask(LSX) Negative(m@@OPTSTR_LSX@@) +Enable LoongArch SIMD Extension (LSX). ;; Base target models (implies ISA & tune parameters) Enum @@ -125,11 +128,14 @@ Target RejectNegative Joined ToLower Enum(abi_base) Var(la_opt_abi_base) Init(M_ Variable int la_opt_abi_ext = M_OPTION_NOT_SEEN - mbranch-cost= Target RejectNegative Joined UInteger Var(loongarch_branch_cost) -mbranch-cost=COST Set the cost of branches to roughly COST instructions. +mmemvec-cost= +Target RejectNegative Joined UInteger Var(loongarch_vector_access_cost) IntegerRange(1, 5) +mmemvec-cost=COST Set the cost of vector memory access instructions. + mcheck-zero-division Target Mask(CHECK_ZERO_DIV) Trap on integer divide by zero. diff --git a/gcc/config/loongarch/loongarch-c.cc b/gcc/config/loongarch/loongarch-c.cc index 67911b78f28..b065921adc3 100644 --- a/gcc/config/loongarch/loongarch-c.cc +++ b/gcc/config/loongarch/loongarch-c.cc @@ -99,6 +99,13 @@ loongarch_cpu_cpp_builtins (cpp_reader *pfile) else builtin_define ("__loongarch_frlen=0"); + if (ISA_HAS_LSX) + { + builtin_define ("__loongarch_simd"); + builtin_define ("__loongarch_sx"); + builtin_define ("__loongarch_sx_width=128"); + } + /* Native Data Sizes. */ builtin_define_with_int_value ("_LOONGARCH_SZINT", INT_TYPE_SIZE); builtin_define_with_int_value ("_LOONGARCH_SZLONG", LONG_TYPE_SIZE); diff --git a/gcc/config/loongarch/loongarch-def.c b/gcc/config/loongarch/loongarch-def.c index 6729c857f7c..28e24c62249 100644 --- a/gcc/config/loongarch/loongarch-def.c +++ b/gcc/config/loongarch/loongarch-def.c @@ -49,10 +49,12 @@ loongarch_cpu_default_isa[N_ARCH_TYPES] = { [CPU_LOONGARCH64] = { .base = ISA_BASE_LA64V100, .fpu = ISA_EXT_FPU64, + .simd = 0, }, [CPU_LA464] = { .base = ISA_BASE_LA64V100, .fpu = ISA_EXT_FPU64, + .simd = ISA_EXT_SIMD_LSX, }, }; @@ -147,6 +149,7 @@ loongarch_isa_ext_strings[N_ISA_EXT_TYPES] = { [ISA_EXT_FPU64] = STR_ISA_EXT_FPU64, [ISA_EXT_FPU32] = STR_ISA_EXT_FPU32, [ISA_EXT_NOFPU] = STR_ISA_EXT_NOFPU, + [ISA_EXT_SIMD_LSX] = OPTSTR_LSX, }; const char* @@ -176,6 +179,7 @@ loongarch_switch_strings[] = { [SW_SOFT_FLOAT] = OPTSTR_SOFT_FLOAT, [SW_SINGLE_FLOAT] = OPTSTR_SINGLE_FLOAT, [SW_DOUBLE_FLOAT] = OPTSTR_DOUBLE_FLOAT, + [SW_LSX] = OPTSTR_LSX, }; diff --git a/gcc/config/loongarch/loongarch-def.h b/gcc/config/loongarch/loongarch-def.h index fb8bb88eb52..f34cffcfb9b 100644 --- a/gcc/config/loongarch/loongarch-def.h +++ b/gcc/config/loongarch/loongarch-def.h @@ -63,7 +63,8 @@ extern const char* loongarch_isa_ext_strings[]; #define ISA_EXT_FPU32 1 #define ISA_EXT_FPU64 2 #define N_ISA_EXT_FPU_TYPES 3 -#define N_ISA_EXT_TYPES 3 +#define ISA_EXT_SIMD_LSX 3 +#define N_ISA_EXT_TYPES 4 /* enum abi_base */ extern const char* loongarch_abi_base_strings[]; @@ -97,7 +98,8 @@ extern const char* loongarch_switch_strings[]; #define SW_SOFT_FLOAT 0 #define SW_SINGLE_FLOAT 1 #define SW_DOUBLE_FLOAT 2 -#define N_SWITCH_TYPES 3 +#define SW_LSX 3 +#define N_SWITCH_TYPES 4 /* The common default value for variables whose assignments are triggered by command-line options. */ @@ -111,6 +113,7 @@ struct loongarch_isa { unsigned char base; /* ISA_BASE_ */ unsigned char fpu; /* ISA_EXT_FPU_ */ + unsigned char simd; /* ISA_EXT_SIMD_ */ }; struct loongarch_abi diff --git a/gcc/config/loongarch/loongarch-driver.cc b/gcc/config/loongarch/loongarch-driver.cc index 11ce082417f..aa5011bd86a 100644 --- a/gcc/config/loongarch/loongarch-driver.cc +++ b/gcc/config/loongarch/loongarch-driver.cc @@ -160,6 +160,10 @@ driver_get_normalized_m_opts (int argc, const char **argv) APPEND_LTR (" % promotes %<%s%> to %<%s%s%>", + OPTSTR_ISA_EXT_FPU, loongarch_isa_ext_strings[t.isa.fpu], + OPTSTR_ISA_EXT_FPU, loongarch_isa_ext_strings[ISA_EXT_FPU64]); + + t.isa.fpu = ISA_EXT_FPU64; + } + else if (on (SOFT_FLOAT) || on (SINGLE_FLOAT)) + { + if (constrained.simd) + inform (UNKNOWN_LOCATION, + "%<-m%s%> is disabled by %<-m%s%>, because it requires %<%s%s%>", + loongarch_switch_strings[simd_switch], + loongarch_switch_strings[on_switch], + OPTSTR_ISA_EXT_FPU, loongarch_isa_ext_strings[ISA_EXT_FPU64]); + + /* SIMD that comes from arch default. */ + t.isa.simd = 0; + } + else + { + /* -mfpu=0 / -mfpu=32 is set. */ + if (constrained.simd) + fatal_error (UNKNOWN_LOCATION, + "%<-m%s=%s%> conflicts with %<-m%s%>," + "which requires %<%s%s%>", + OPTSTR_ISA_EXT_FPU, loongarch_isa_ext_strings[t.isa.fpu], + loongarch_switch_strings[simd_switch], + OPTSTR_ISA_EXT_FPU, + loongarch_isa_ext_strings[ISA_EXT_FPU64]); + + /* Same as above. */ + t.isa.simd = 0; + } + } /* 4. ABI-ISA compatibility */ /* Note: @@ -530,6 +599,17 @@ isa_str (const struct loongarch_isa *isa, char separator) APPEND_STRING (OPTSTR_ISA_EXT_FPU) APPEND_STRING (loongarch_isa_ext_strings[isa->fpu]) } + + switch (isa->simd) + { + case ISA_EXT_SIMD_LSX: + APPEND1 (separator); + APPEND_STRING (loongarch_isa_ext_strings[isa->simd]); + break; + + default: + gcc_assert (isa->simd == 0); + } APPEND1 ('\0') /* Add more here. */ diff --git a/gcc/config/loongarch/loongarch-opts.h b/gcc/config/loongarch/loongarch-opts.h index b1ff54426e4..d067c05dfc9 100644 --- a/gcc/config/loongarch/loongarch-opts.h +++ b/gcc/config/loongarch/loongarch-opts.h @@ -66,6 +66,7 @@ loongarch_config_target (struct loongarch_target *target, || la_target.abi.base == ABI_BASE_LP64F \ || la_target.abi.base == ABI_BASE_LP64S) +#define ISA_HAS_LSX (la_target.isa.simd == ISA_EXT_SIMD_LSX) #define TARGET_ARCH_NATIVE (la_target.cpu_arch == CPU_NATIVE) #define LARCH_ACTUAL_ARCH (TARGET_ARCH_NATIVE \ ? (la_target.cpu_native < N_ARCH_TYPES \ diff --git a/gcc/config/loongarch/loongarch-str.h b/gcc/config/loongarch/loongarch-str.h index af2e82a321f..6fa1b1571c5 100644 --- a/gcc/config/loongarch/loongarch-str.h +++ b/gcc/config/loongarch/loongarch-str.h @@ -42,6 +42,8 @@ along with GCC; see the file COPYING3. If not see #define OPTSTR_SINGLE_FLOAT "single-float" #define OPTSTR_DOUBLE_FLOAT "double-float" +#define OPTSTR_LSX "lsx" + #define OPTSTR_ABI_BASE "abi" #define STR_ABI_BASE_LP64D "lp64d" #define STR_ABI_BASE_LP64F "lp64f" diff --git a/gcc/config/loongarch/loongarch.opt b/gcc/config/loongarch/loongarch.opt index 68018ade73f..5c7e6d37220 100644 --- a/gcc/config/loongarch/loongarch.opt +++ b/gcc/config/loongarch/loongarch.opt @@ -83,6 +83,9 @@ mdouble-float Target Driver RejectNegative Var(la_opt_switches) Mask(FORCE_F64) Negative(msoft-float) Allow hardware floating-point instructions to cover both 32-bit and 64-bit operations. +mlsx +Target RejectNegative Var(la_opt_switches) Mask(LSX) Negative(mlsx) +Enable LoongArch SIMD Extension (LSX). ;; Base target models (implies ISA & tune parameters) Enum @@ -132,11 +135,14 @@ Target RejectNegative Joined ToLower Enum(abi_base) Var(la_opt_abi_base) Init(M_ Variable int la_opt_abi_ext = M_OPTION_NOT_SEEN - mbranch-cost= Target RejectNegative Joined UInteger Var(loongarch_branch_cost) -mbranch-cost=COST Set the cost of branches to roughly COST instructions. +mmemvec-cost= +Target RejectNegative Joined UInteger Var(loongarch_vector_access_cost) IntegerRange(1, 5) +mmemvec-cost=COST Set the cost of vector memory access instructions. + mcheck-zero-division Target Mask(CHECK_ZERO_DIV) Trap on integer divide by zero. -- 2.36.0