From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by sourceware.org (Postfix) with ESMTPS id 9B1873858C2B for ; Thu, 20 Jul 2023 06:38:13 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 9B1873858C2B Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1689835093; x=1721371093; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=qpNeNDh+KwKUN2NUY66bYVGYUSibBjQSwKWpBJhFa+U=; b=VsktQsVjCXwjDNrYpiWLX3+XnrewuJ0NcWvo0dY2JBgn2vFa7UklKja8 4f3fPSUCClWFNJ0ouQVC7cOTLAZvZkqGU9yuYrk+APa/sxVtnpUZo4huT Xr8jFH9oWpmnuK4fGWFo2jeJDQVcTDtAorK1tyEIv86tfmkM8PaVIB37Q wFcEAmfsU+9+olUO2PmsTyxX+nNVwZs+aDabqXWw4QurzDhSjEG4UZAwF qa3nD90HTzM2f3FwRuTX2YNvHG4nrBFAe3bmaL5zr/qIElcb6JmOafJew 4HC1l848xHvIF5fzRYb/wedbxffs4LAT+0itlG6bghQiREHv3TZwUat92 g==; X-IronPort-AV: E=McAfee;i="6600,9927,10776"; a="430416307" X-IronPort-AV: E=Sophos;i="6.01,218,1684825200"; d="scan'208";a="430416307" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Jul 2023 23:32:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10776"; a="970916206" X-IronPort-AV: E=Sophos;i="6.01,218,1684825200"; d="scan'208";a="970916206" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga006.fm.intel.com with ESMTP; 19 Jul 2023 23:32:53 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id B9E511005631; Thu, 20 Jul 2023 14:32:52 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, jeffreyalaw@gmail.com, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Align the pattern format in vector.md Date: Thu, 20 Jul 2023 14:32:50 +0800 Message-Id: <20230720063250.1910048-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-8.0 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_ASCII_DIVIDERS,MEDICAL_SUBJECT,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Pan Li There are some format-unaligned pattern in vector.md, this patch would like to align the format for these patterns. Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/vector.md: Align pattern format. --- gcc/config/riscv/vector.md | 850 +++++++++++++------------------------ 1 file changed, 297 insertions(+), 553 deletions(-) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 69680de2600..fcff3ee3a17 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -669,61 +669,45 @@ (define_attr "avl_type" "" ;; Defines rounding mode of an fixed-point operation. (define_attr "vxrm_mode" "rnu,rne,rdn,rod,none" - (cond - [ - (eq_attr "type" "vsalu,vaalu,vsmul,vsshift,vnclip") - (cond - [ - (match_test "INTVAL (operands[9]) == riscv_vector::VXRM_RNU") - (const_string "rnu") - - (match_test "INTVAL (operands[9]) == riscv_vector::VXRM_RNE") - (const_string "rne") - - (match_test "INTVAL (operands[9]) == riscv_vector::VXRM_RDN") - (const_string "rdn") - - (match_test "INTVAL (operands[9]) == riscv_vector::VXRM_ROD") - (const_string "rod") - ] - (const_string "none") - ) - ] - (const_string "none") - ) -) + (cond [(eq_attr "type" "vsalu,vaalu,vsmul,vsshift,vnclip") + (cond + [(match_test "INTVAL (operands[9]) == riscv_vector::VXRM_RNU") + (const_string "rnu") + + (match_test "INTVAL (operands[9]) == riscv_vector::VXRM_RNE") + (const_string "rne") + + (match_test "INTVAL (operands[9]) == riscv_vector::VXRM_RDN") + (const_string "rdn") + + (match_test "INTVAL (operands[9]) == riscv_vector::VXRM_ROD") + (const_string "rod")] + (const_string "none"))] + (const_string "none"))) ;; Defines rounding mode of an floating-point operation. (define_attr "frm_mode" "rne,rtz,rdn,rup,rmm,dyn,dyn_exit,none" - (cond - [ - (eq_attr "type" "vfalu") - (cond - [ - (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RNE") - (const_string "rne") - - (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RTZ") - (const_string "rtz") - - (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RDN") - (const_string "rdn") - - (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RUP") - (const_string "rup") - - (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RMM") - (const_string "rmm") - - (match_test "INTVAL (operands[9]) == riscv_vector::FRM_DYN") - (const_string "dyn") - ] - (const_string "none") - ) - ] - (const_string "none") - ) -) + (cond [(eq_attr "type" "vfalu") + (cond + [(match_test "INTVAL (operands[9]) == riscv_vector::FRM_RNE") + (const_string "rne") + + (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RTZ") + (const_string "rtz") + + (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RDN") + (const_string "rdn") + + (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RUP") + (const_string "rup") + + (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RMM") + (const_string "rmm") + + (match_test "INTVAL (operands[9]) == riscv_vector::FRM_DYN") + (const_string "dyn")] + (const_string "none"))] + (const_string "none"))) ;; ----------------------------------------------------------------- ;; ---- Miscellaneous Operations @@ -7631,583 +7615,343 @@ (define_insn "@pred_rod_trunc" ;; Integer Reduction for QI (define_insn "@pred_reduc_" - [ - (set - (match_operand:VQI_LMUL1 0 "register_operand" "=vr, vr") - (unspec:VQI_LMUL1 - [ - (unspec: - [ - (match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM) - ] UNSPEC_VPREDICATE - ) - (any_reduc:VQI - (vec_duplicate:VQI - (vec_select: - (match_operand:VQI_LMUL1 4 "register_operand" " vr, vr") - (parallel [(const_int 0)]) - ) - ) - (match_operand:VQI 3 "register_operand" " vr, vr") - ) - (match_operand:VQI_LMUL1 2 "vector_merge_operand" " vu, 0") - ] UNSPEC_REDUC - ) - ) - ] + [(set (match_operand:VQI_LMUL1 0 "register_operand" "=vr, vr") + (unspec:VQI_LMUL1 + [(unspec: + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (any_reduc:VQI + (vec_duplicate:VQI + (vec_select: + (match_operand:VQI_LMUL1 4 "register_operand" " vr, vr") + (parallel [(const_int 0)]))) + (match_operand:VQI 3 "register_operand" " vr, vr")) + (match_operand:VQI_LMUL1 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))] "TARGET_VECTOR" "vred.vs\t%0,%3,%4%p1" - [ - (set_attr "type" "vired") - (set_attr "mode" "") - ] -) + [(set_attr "type" "vired") + (set_attr "mode" "")]) ;; Integer Reduction for HI (define_insn "@pred_reduc_" - [ - (set - (match_operand:VHI_LMUL1 0 "register_operand" "=vr, vr") - (unspec:VHI_LMUL1 - [ - (unspec: - [ - (match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM) - ] UNSPEC_VPREDICATE - ) - (any_reduc:VHI - (vec_duplicate:VHI - (vec_select: - (match_operand:VHI_LMUL1 4 "register_operand" " vr, vr") - (parallel [(const_int 0)]) - ) - ) - (match_operand:VHI 3 "register_operand" " vr, vr") - ) - (match_operand:VHI_LMUL1 2 "vector_merge_operand" " vu, 0") - ] UNSPEC_REDUC - ) - ) - ] + [(set (match_operand:VHI_LMUL1 0 "register_operand" "=vr, vr") + (unspec:VHI_LMUL1 + [(unspec: + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (any_reduc:VHI + (vec_duplicate:VHI + (vec_select: + (match_operand:VHI_LMUL1 4 "register_operand" " vr, vr") + (parallel [(const_int 0)]))) + (match_operand:VHI 3 "register_operand" " vr, vr")) + (match_operand:VHI_LMUL1 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))] "TARGET_VECTOR" "vred.vs\t%0,%3,%4%p1" - [ - (set_attr "type" "vired") - (set_attr "mode" "") - ] -) + [(set_attr "type" "vired") + (set_attr "mode" "")]) ;; Integer Reduction for SI (define_insn "@pred_reduc_" - [ - (set - (match_operand:VSI_LMUL1 0 "register_operand" "=vr, vr") - (unspec:VSI_LMUL1 - [ - (unspec: - [ - (match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM) - ] UNSPEC_VPREDICATE - ) - (any_reduc:VSI - (vec_duplicate:VSI - (vec_select: - (match_operand:VSI_LMUL1 4 "register_operand" " vr, vr") - (parallel [(const_int 0)]) - ) - ) - (match_operand:VSI 3 "register_operand" " vr, vr") - ) - (match_operand:VSI_LMUL1 2 "vector_merge_operand" " vu, 0") - ] UNSPEC_REDUC - ) - ) - ] + [(set (match_operand:VSI_LMUL1 0 "register_operand" "=vr, vr") + (unspec:VSI_LMUL1 + [(unspec: + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (any_reduc:VSI + (vec_duplicate:VSI + (vec_select: + (match_operand:VSI_LMUL1 4 "register_operand" " vr, vr") + (parallel [(const_int 0)]))) + (match_operand:VSI 3 "register_operand" " vr, vr")) + (match_operand:VSI_LMUL1 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))] "TARGET_VECTOR" "vred.vs\t%0,%3,%4%p1" - [ - (set_attr "type" "vired") - (set_attr "mode" "") - ] -) + [(set_attr "type" "vired") + (set_attr "mode" "")]) ;; Integer Reduction for DI (define_insn "@pred_reduc_" - [ - (set - (match_operand:VDI_LMUL1 0 "register_operand" "=vr, vr") - (unspec:VDI_LMUL1 - [ - (unspec: - [ - (match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM) - ] UNSPEC_VPREDICATE - ) - (any_reduc:VDI - (vec_duplicate:VDI - (vec_select: - (match_operand:VDI_LMUL1 4 "register_operand" " vr, vr") - (parallel [(const_int 0)]) - ) - ) - (match_operand:VDI 3 "register_operand" " vr, vr") - ) - (match_operand:VDI_LMUL1 2 "vector_merge_operand" " vu, 0") - ] UNSPEC_REDUC - ) - ) - ] + [(set (match_operand:VDI_LMUL1 0 "register_operand" "=vr, vr") + (unspec:VDI_LMUL1 + [(unspec: + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (any_reduc:VDI + (vec_duplicate:VDI + (vec_select: + (match_operand:VDI_LMUL1 4 "register_operand" " vr, vr") + (parallel [(const_int 0)]))) + (match_operand:VDI 3 "register_operand" " vr, vr")) + (match_operand:VDI_LMUL1 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))] "TARGET_VECTOR" "vred.vs\t%0,%3,%4%p1" - [ - (set_attr "type" "vired") - (set_attr "mode" "") - ] -) + [(set_attr "type" "vired") + (set_attr "mode" "")]) ;; Integer Reduction Widen for QI, HI = QI op HI (define_insn "@pred_widen_reduc_plus" - [ - (set - (match_operand:VHI_LMUL1 0 "register_operand" "=&vr,&vr") - (unspec:VHI_LMUL1 - [ - (unspec: - [ - (match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM) - ] UNSPEC_VPREDICATE - ) - (match_operand:VQI 3 "register_operand" " vr, vr") - (match_operand:VHI_LMUL1 4 "register_operand" " vr, vr") - (match_operand:VHI_LMUL1 2 "vector_merge_operand" " vu, 0") - ] WREDUC - ) - ) - ] + [(set (match_operand:VHI_LMUL1 0 "register_operand" "=&vr,&vr") + (unspec:VHI_LMUL1 + [(unspec: + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (match_operand:VQI 3 "register_operand" " vr, vr") + (match_operand:VHI_LMUL1 4 "register_operand" " vr, vr") + (match_operand:VHI_LMUL1 2 "vector_merge_operand" " vu, 0")] WREDUC))] "TARGET_VECTOR" "vwredsum.vs\t%0,%3,%4%p1" - [ - (set_attr "type" "viwred") - (set_attr "mode" "") - ] -) + [(set_attr "type" "viwred") + (set_attr "mode" "")]) ;; Integer Reduction Widen for HI, SI = HI op SI (define_insn "@pred_widen_reduc_plus" - [ - (set - (match_operand:VSI_LMUL1 0 "register_operand" "=&vr,&vr") - (unspec:VSI_LMUL1 - [ - (unspec: - [ - (match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM) - ] UNSPEC_VPREDICATE - ) - (match_operand:VHI 3 "register_operand" " vr, vr") - (match_operand:VSI_LMUL1 4 "register_operand" " vr, vr") - (match_operand:VSI_LMUL1 2 "vector_merge_operand" " vu, 0") - ] WREDUC - ) - ) - ] + [(set (match_operand:VSI_LMUL1 0 "register_operand" "=&vr,&vr") + (unspec:VSI_LMUL1 + [(unspec: + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (match_operand:VHI 3 "register_operand" " vr, vr") + (match_operand:VSI_LMUL1 4 "register_operand" " vr, vr") + (match_operand:VSI_LMUL1 2 "vector_merge_operand" " vu, 0")] WREDUC))] "TARGET_VECTOR" "vwredsum.vs\t%0,%3,%4%p1" - [ - (set_attr "type" "viwred") - (set_attr "mode" "") - ] -) + [(set_attr "type" "viwred") + (set_attr "mode" "")]) ;; Integer Reduction Widen for SI, DI = SI op DI (define_insn "@pred_widen_reduc_plus" - [ - (set - (match_operand:VDI_LMUL1 0 "register_operand" "=&vr,&vr") - (unspec:VDI_LMUL1 - [ - (unspec: - [ - (match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM) - ] UNSPEC_VPREDICATE - ) - (match_operand:VSI 3 "register_operand" " vr, vr") - (match_operand:VDI_LMUL1 4 "register_operand" " vr, vr") - (match_operand:VDI_LMUL1 2 "vector_merge_operand" " vu, 0") - ] WREDUC - ) - ) - ] + [(set (match_operand:VDI_LMUL1 0 "register_operand" "=&vr,&vr") + (unspec:VDI_LMUL1 + [(unspec: + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (match_operand:VSI 3 "register_operand" " vr, vr") + (match_operand:VDI_LMUL1 4 "register_operand" " vr, vr") + (match_operand:VDI_LMUL1 2 "vector_merge_operand" " vu, 0")] WREDUC))] "TARGET_VECTOR" "vwredsum.vs\t%0,%3,%4%p1" - [ - (set_attr "type" "viwred") - (set_attr "mode" "") - ] -) + [(set_attr "type" "viwred") + (set_attr "mode" "")]) ;; Float Reduction for HF (define_insn "@pred_reduc_" - [ - (set - (match_operand:VHF_LMUL1 0 "register_operand" "=vr, vr") - (unspec:VHF_LMUL1 - [ - (unspec: - [ - (match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM) - ] UNSPEC_VPREDICATE - ) - (any_reduc:VHF - (vec_duplicate:VHF - (vec_select: - (match_operand:VHF_LMUL1 4 "register_operand" " vr, vr") - (parallel [(const_int 0)]) - ) - ) - (match_operand:VHF 3 "register_operand" " vr, vr") - ) - (match_operand:VHF_LMUL1 2 "vector_merge_operand" " vu, 0") - ] UNSPEC_REDUC - ) - ) - ] + [(set (match_operand:VHF_LMUL1 0 "register_operand" "=vr, vr") + (unspec:VHF_LMUL1 + [(unspec: + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (any_reduc:VHF + (vec_duplicate:VHF + (vec_select: + (match_operand:VHF_LMUL1 4 "register_operand" " vr, vr") + (parallel [(const_int 0)]))) + (match_operand:VHF 3 "register_operand" " vr, vr")) + (match_operand:VHF_LMUL1 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))] "TARGET_VECTOR" "vfred.vs\t%0,%3,%4%p1" - [ - (set_attr "type" "vfredu") - (set_attr "mode" "") - ] -) + [(set_attr "type" "vfredu") + (set_attr "mode" "")]) ;; Float Reduction for SF (define_insn "@pred_reduc_" - [ - (set - (match_operand:VSF_LMUL1 0 "register_operand" "=vr, vr") + [(set (match_operand:VSF_LMUL1 0 "register_operand" "=vr, vr") (unspec:VSF_LMUL1 - [ - (unspec: - [ - (match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM) - ] UNSPEC_VPREDICATE - ) - (any_reduc:VSF + [(unspec: + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (any_reduc:VSF (vec_duplicate:VSF (vec_select: (match_operand:VSF_LMUL1 4 "register_operand" " vr, vr") - (parallel [(const_int 0)]) - ) - ) - (match_operand:VSF 3 "register_operand" " vr, vr") - ) - (match_operand:VSF_LMUL1 2 "vector_merge_operand" " vu, 0") - ] UNSPEC_REDUC - ) - ) - ] + (parallel [(const_int 0)]))) + (match_operand:VSF 3 "register_operand" " vr, vr")) + (match_operand:VSF_LMUL1 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))] "TARGET_VECTOR" "vfred.vs\t%0,%3,%4%p1" - [ - (set_attr "type" "vfredu") - (set_attr "mode" "") - ] -) + [(set_attr "type" "vfredu") + (set_attr "mode" "")]) ;; Float Reduction for DF (define_insn "@pred_reduc_" - [ - (set - (match_operand:VDF_LMUL1 0 "register_operand" "=vr, vr") - (unspec:VDF_LMUL1 - [ - (unspec: - [ - (match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM) - ] UNSPEC_VPREDICATE - ) - (any_reduc:VDF - (vec_duplicate:VDF - (vec_select: - (match_operand:VDF_LMUL1 4 "register_operand" " vr, vr") - (parallel [(const_int 0)]) - ) - ) - (match_operand:VDF 3 "register_operand" " vr, vr") - ) - (match_operand:VDF_LMUL1 2 "vector_merge_operand" " vu, 0") - ] UNSPEC_REDUC - ) - ) - ] + [(set (match_operand:VDF_LMUL1 0 "register_operand" "=vr, vr") + (unspec:VDF_LMUL1 + [(unspec: + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (any_reduc:VDF + (vec_duplicate:VDF + (vec_select: + (match_operand:VDF_LMUL1 4 "register_operand" " vr, vr") + (parallel [(const_int 0)]))) + (match_operand:VDF 3 "register_operand" " vr, vr")) + (match_operand:VDF_LMUL1 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))] "TARGET_VECTOR" "vfred.vs\t%0,%3,%4%p1" - [ - (set_attr "type" "vfredu") - (set_attr "mode" "") - ] -) + [(set_attr "type" "vfredu") + (set_attr "mode" "")]) ;; Float Ordered Reduction Sum for HF (define_insn "@pred_reduc_plus" - [ - (set - (match_operand:VHF_LMUL1 0 "register_operand" "=vr,vr") - (unspec:VHF_LMUL1 - [ - (unspec:VHF_LMUL1 - [ - (unspec: - [ - (match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM) - (reg:SI FRM_REGNUM) - ] UNSPEC_VPREDICATE - ) - (plus:VHF - (vec_duplicate:VHF - (vec_select: - (match_operand:VHF_LMUL1 4 "register_operand" " vr, vr") - (parallel [(const_int 0)]) - ) - ) - (match_operand:VHF 3 "register_operand" " vr, vr") - ) - (match_operand:VHF_LMUL1 2 "vector_merge_operand" " vu, 0") - ] UNSPEC_REDUC - ) - ] ORDER - ) - ) - ] + [(set (match_operand:VHF_LMUL1 0 "register_operand" "=vr,vr") + (unspec:VHF_LMUL1 + [(unspec:VHF_LMUL1 + [(unspec: + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) + (plus:VHF + (vec_duplicate:VHF + (vec_select: + (match_operand:VHF_LMUL1 4 "register_operand" " vr, vr") + (parallel [(const_int 0)]))) + (match_operand:VHF 3 "register_operand" " vr, vr")) + (match_operand:VHF_LMUL1 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC)] ORDER))] "TARGET_VECTOR" "vfredsum.vs\t%0,%3,%4%p1" - [ - (set_attr "type" "vfred") - (set_attr "mode" "") - ] -) + [(set_attr "type" "vfred") + (set_attr "mode" "")]) ;; Float Ordered Reduction Sum for SF (define_insn "@pred_reduc_plus" - [ - (set - (match_operand:VSF_LMUL1 0 "register_operand" "=vr,vr") - (unspec:VSF_LMUL1 - [ - (unspec:VSF_LMUL1 - [ - (unspec: - [ - (match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM) - (reg:SI FRM_REGNUM) - ] UNSPEC_VPREDICATE - ) - (plus:VSF - (vec_duplicate:VSF - (vec_select: - (match_operand:VSF_LMUL1 4 "register_operand" " vr, vr") - (parallel [(const_int 0)]) - ) - ) - (match_operand:VSF 3 "register_operand" " vr, vr") - ) - (match_operand:VSF_LMUL1 2 "vector_merge_operand" " vu, 0") - ] UNSPEC_REDUC - ) - ] ORDER - ) - ) - ] + [(set (match_operand:VSF_LMUL1 0 "register_operand" "=vr,vr") + (unspec:VSF_LMUL1 + [(unspec:VSF_LMUL1 + [(unspec: + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) + (plus:VSF + (vec_duplicate:VSF + (vec_select: + (match_operand:VSF_LMUL1 4 "register_operand" " vr, vr") + (parallel [(const_int 0)]))) + (match_operand:VSF 3 "register_operand" " vr, vr")) + (match_operand:VSF_LMUL1 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC)] ORDER))] "TARGET_VECTOR" "vfredsum.vs\t%0,%3,%4%p1" - [ - (set_attr "type" "vfred") - (set_attr "mode" "") - ] -) + [(set_attr "type" "vfred") + (set_attr "mode" "")]) ;; Float Ordered Reduction Sum for DF (define_insn "@pred_reduc_plus" - [ - (set - (match_operand:VDF_LMUL1 0 "register_operand" "=vr,vr") - (unspec:VDF_LMUL1 - [ - (unspec:VDF_LMUL1 - [ - (unspec: - [ - (match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM) - (reg:SI FRM_REGNUM) - ] UNSPEC_VPREDICATE - ) - (plus:VDF - (vec_duplicate:VDF - (vec_select: - (match_operand:VDF_LMUL1 4 "register_operand" " vr, vr") - (parallel [(const_int 0)]) - ) - ) - (match_operand:VDF 3 "register_operand" " vr, vr") - ) - (match_operand:VDF_LMUL1 2 "vector_merge_operand" " vu, 0") - ] UNSPEC_REDUC - ) - ] ORDER - ) - ) - ] + [(set (match_operand:VDF_LMUL1 0 "register_operand" "=vr,vr") + (unspec:VDF_LMUL1 + [(unspec:VDF_LMUL1 + [(unspec: + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) + (plus:VDF + (vec_duplicate:VDF + (vec_select: + (match_operand:VDF_LMUL1 4 "register_operand" " vr, vr") + (parallel [(const_int 0)]))) + (match_operand:VDF 3 "register_operand" " vr, vr")) + (match_operand:VDF_LMUL1 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC)] ORDER))] "TARGET_VECTOR" "vfredsum.vs\t%0,%3,%4%p1" - [ - (set_attr "type" "vfred") - (set_attr "mode" "") - ] -) + [(set_attr "type" "vfred") + (set_attr "mode" "")]) ;; Float Widen Reduction for HF, aka SF = HF op SF (define_insn "@pred_widen_reduc_plus" - [ - (set - (match_operand:VSF_LMUL1 0 "register_operand" "=&vr, &vr") - (unspec:VSF_LMUL1 - [ - (unspec:VSF_LMUL1 - [ - (unspec: - [ - (match_operand: 1 "vector_merge_operand" "vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM) - (reg:SI FRM_REGNUM) - ] UNSPEC_VPREDICATE - ) - (match_operand:VHF 3 "register_operand" " vr, vr") - (match_operand:VSF_LMUL1 4 "register_operand" " vr, vr") - (match_operand:VSF_LMUL1 2 "vector_merge_operand" " vu, 0") - ] UNSPEC_WREDUC_SUM - ) - ] ORDER - ) - ) - ] + [(set (match_operand:VSF_LMUL1 0 "register_operand" "=&vr, &vr") + (unspec:VSF_LMUL1 + [(unspec:VSF_LMUL1 + [(unspec: + [(match_operand: 1 "vector_merge_operand" "vmWc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) + (match_operand:VHF 3 "register_operand" " vr, vr") + (match_operand:VSF_LMUL1 4 "register_operand" " vr, vr") + (match_operand:VSF_LMUL1 2 "vector_merge_operand" " vu, 0")] UNSPEC_WREDUC_SUM)] ORDER))] "TARGET_VECTOR" "vfwredsum.vs\t%0,%3,%4%p1" - [ - (set_attr "type" "vfwred") - (set_attr "mode" "") - ] -) + [(set_attr "type" "vfwred") + (set_attr "mode" "")]) ;; Float Widen Reduction for SF, aka DF = SF * DF (define_insn "@pred_widen_reduc_plus" - [ - (set - (match_operand:VDF_LMUL1 0 "register_operand" "=&vr, &vr") - (unspec:VDF_LMUL1 - [ - (unspec:VDF_LMUL1 - [ - (unspec: - [ - (match_operand: 1 "vector_merge_operand" "vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM) - (reg:SI FRM_REGNUM) - ] UNSPEC_VPREDICATE - ) - (match_operand:VSF 3 "register_operand" " vr, vr") - (match_operand:VDF_LMUL1 4 "register_operand" " vr, vr") - (match_operand:VDF_LMUL1 2 "vector_merge_operand" " vu, 0") - ] UNSPEC_WREDUC_SUM - ) - ] ORDER - ) - ) - ] + [(set (match_operand:VDF_LMUL1 0 "register_operand" "=&vr, &vr") + (unspec:VDF_LMUL1 + [(unspec:VDF_LMUL1 + [(unspec: + [(match_operand: 1 "vector_merge_operand" "vmWc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) + (match_operand:VSF 3 "register_operand" " vr, vr") + (match_operand:VDF_LMUL1 4 "register_operand" " vr, vr") + (match_operand:VDF_LMUL1 2 "vector_merge_operand" " vu, 0")] UNSPEC_WREDUC_SUM)] ORDER))] "TARGET_VECTOR" "vfwredsum.vs\t%0,%3,%4%p1" - [ - (set_attr "type" "vfwred") - (set_attr "mode" "") - ] -) + [(set_attr "type" "vfwred") + (set_attr "mode" "")]) ;; ------------------------------------------------------------------------------- ;; ---- Predicated permutation operations -- 2.34.1