From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by sourceware.org (Postfix) with ESMTPS id 36E1F3858CDB for ; Thu, 20 Jul 2023 08:35:35 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 36E1F3858CDB Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1689842135; x=1721378135; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=cOpjT8yL+T9m6QfGXf4RIWw3NDp8EBHi1gwFvqFWFu4=; b=UsvgwH4faCXFLX0h1gVhxiQB+bKCWmBmcu7v/cShQlVieij6oNUSrbEN 4uT6BAN4qNVRnsV0AGhUfnFkFQlKLWpMNVTquisxc2V2Xfx420mMlraPL 5DLajtnAYwrToVXxwq70v28wiNZYwCjhWs0/dtQp6Yuu035TwxBBAFHoZ YFPoCicKtwqR9z7MIbJ1+EzAcSsxYcjEXjj0Xb8gr8VF77Ua+wQVmV4Gn pWPsm9miFptiW4vSlMf2A7Sw97tESZ8pAfRWKvo2vDME73dEOmDc1VP7/ lnSJXgb8RNW5Qk2rg5gbyscc7i0TELlh2iL5FRq50Hsco8Pvg137/wj75 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10776"; a="351538190" X-IronPort-AV: E=Sophos;i="6.01,218,1684825200"; d="scan'208";a="351538190" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jul 2023 01:35:33 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10776"; a="724310685" X-IronPort-AV: E=Sophos;i="6.01,218,1684825200"; d="scan'208";a="724310685" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by orsmga002.jf.intel.com with ESMTP; 20 Jul 2023 01:35:32 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id 51A2710056A0; Thu, 20 Jul 2023 16:35:31 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Fix one incorrect match operand for RVV reduction Date: Thu, 20 Jul 2023 16:35:30 +0800 Message-Id: <20230720083530.3260344-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Pan Li There are 2 of the RVV reduction pattern mask operand takes vector_merge_operand instead of vector_mask_operand by mistake. This patch would like to fix this. Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/vector.md: Fix incorrect match_operand. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr110299-1.c: Adjust tests. * gcc.target/riscv/rvv/base/pr110299-2.c: Ditto. --- gcc/config/riscv/vector.md | 4 ++-- gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-1.c | 4 ++-- gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-2.c | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index fcff3ee3a17..f745888127c 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -7915,7 +7915,7 @@ (define_insn "@pred_widen_reduc_plus" (unspec:VSF_LMUL1 [(unspec:VSF_LMUL1 [(unspec: - [(match_operand: 1 "vector_merge_operand" "vmWc1,vmWc1") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") (match_operand 5 "vector_length_operand" " rK, rK") (match_operand 6 "const_int_operand" " i, i") (match_operand 7 "const_int_operand" " i, i") @@ -7937,7 +7937,7 @@ (define_insn "@pred_widen_reduc_plus" (unspec:VDF_LMUL1 [(unspec:VDF_LMUL1 [(unspec: - [(match_operand: 1 "vector_merge_operand" "vmWc1,vmWc1") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") (match_operand 5 "vector_length_operand" " rK, rK") (match_operand 6 "const_int_operand" " i, i") (match_operand 7 "const_int_operand" " i, i") diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-1.c index d83eea925a7..a903dde34d1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-1.c @@ -3,5 +3,5 @@ #include "pr110299-1.h" -/* { dg-final { scan-assembler-times {vfwredosum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ -/* { dg-final { scan-assembler-times {vfwredusum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vfwredosum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vfwredusum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-2.c index cdcde1b89a4..1254ace58eb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-2.c @@ -4,5 +4,5 @@ #include "pr110299-1.h" #include "pr110299-2.h" -/* { dg-final { scan-assembler-times {vfwredosum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 3 } } */ -/* { dg-final { scan-assembler-times {vfwredusum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 3 } } */ +/* { dg-final { scan-assembler-times {vfwredosum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 3 } } */ +/* { dg-final { scan-assembler-times {vfwredusum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 3 } } */ -- 2.34.1