From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtpbguseast2.qq.com (smtpbguseast2.qq.com [54.204.34.130]) by sourceware.org (Postfix) with ESMTPS id 2E6FC3856092 for ; Thu, 20 Jul 2023 09:01:44 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 2E6FC3856092 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp65t1689843698tdjcekg6 Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.25]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 20 Jul 2023 17:01:37 +0800 (CST) X-QQ-SSF: 01400000000000B0F000000A0000000 X-QQ-FEAT: XPZoqJTqCijpK/ZdZV2yNzn0iMn1Nx9iT6C3seXQNMAlYNNMCpqAQ8AmaDl1u DgbcgVCjbxz64FeKFjOJpE02EhynLyN/iOHhkK99z/Ph8eZyWXTCEa/K/2yHP28hC/yCHzA SFpb67A4r5+I2VX388s4AyGzRuvi1GQw9/Tc+UouGhyiYhyjNddGymLxJxwY4HAovNeP3k7 jAkvmdbCeYfrKA2xTVn9owePv/DAc5APl7oqXRzqsc0au7rEjK6dtjBMM9NdfXt9vl1u5cx +3wHtTLbC0+U2nZWP67RCTBWICN7XoZXc3IAf2NchJsOcDJlFW7RH+7IFVcLITLwhTB+roB tGM5js4mmH0U56ZBDQpnQvOZK4RqxE2G2gFyqeGkauw789Jq8YbnUupPirAAgf61Oill3ON X-QQ-GoodBg: 2 X-BIZMAIL-ID: 12156176601647145867 From: Lehua Ding To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, rdapp.gcc@gmail.com, kito.cheng@gmail.com, palmer@rivosinc.com, jeffreyalaw@gmail.com Subject: [PATCH 3/3] RISC-V: Part-3: Output .variant_cc directive for vector function Date: Thu, 20 Jul 2023 17:01:26 +0800 Message-Id: <20230720090126.2976103-4-lehua.ding@rivai.ai> X-Mailer: git-send-email 2.36.3 In-Reply-To: <20230720090126.2976103-1-lehua.ding@rivai.ai> References: <20230720090126.2976103-1-lehua.ding@rivai.ai> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz6a-0 X-Spam-Status: No, score=-8.7 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_SHORT,RCVD_IN_BARRACUDACENTRAL,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE,URIBL_BLACK autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Functions which follow vector calling convention variant need be annotated by .variant_cc directive according the RISC-V Assembly Programmer's Manual and RISC-V ELF Specification[2]. [1] https://github.com/riscv-non-isa/riscv-asm-manual/blob/master/riscv-asm.md#pseudo-ops [2] https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#dynamic-linking gcc/ChangeLog: * config/riscv/riscv-protos.h (riscv_declare_function_name): Add protos. (riscv_asm_output_alias): Ditto. (riscv_asm_output_external): Ditto. * config/riscv/riscv.cc (riscv_asm_output_variant_cc): Output .variant_cc directive for vector function. (riscv_declare_function_name): Ditto. (riscv_asm_output_alias): Ditto. (riscv_asm_output_external): Ditto. * config/riscv/riscv.h (ASM_DECLARE_FUNCTION_NAME): Implement ASM_DECLARE_FUNCTION_NAME. (ASM_OUTPUT_DEF_FROM_DECLS): Implement ASM_OUTPUT_DEF_FROM_DECLS. (ASM_OUTPUT_EXTERNAL): Implement ASM_OUTPUT_EXTERNAL. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/abi-call-variant_cc.c: New test. --- gcc/config/riscv/riscv-protos.h | 3 ++ gcc/config/riscv/riscv.cc | 48 +++++++++++++++++++ gcc/config/riscv/riscv.h | 15 ++++++ .../riscv/rvv/base/abi-call-variant_cc.c | 39 +++++++++++++++ 4 files changed, 105 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-variant_cc.c diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 52e15e1b5d6..eb62eb46f55 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -101,6 +101,9 @@ extern bool riscv_split_64bit_move_p (rtx, rtx); extern void riscv_split_doubleword_move (rtx, rtx); extern const char *riscv_output_move (rtx, rtx); extern const char *riscv_output_return (); +extern void riscv_declare_function_name (FILE *, const char *, tree); +extern void riscv_asm_output_alias (FILE *, const tree, const tree); +extern void riscv_asm_output_external (FILE *, const tree, const char *); #ifdef RTX_CODE extern void riscv_expand_int_scc (rtx, enum rtx_code, rtx, rtx); diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 1ca3ed42d40..c8879659f1f 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -6740,6 +6740,54 @@ riscv_issue_rate (void) return tune_param->issue_rate; } +/* Output .variant_cc for function symbol which follows vector calling + convention. */ + +static void +riscv_asm_output_variant_cc (FILE *stream, const tree decl, const char *name) +{ + if (TREE_CODE (decl) == FUNCTION_DECL) + { + riscv_cc cc = (riscv_cc) fndecl_abi (decl).id (); + if (cc == RISCV_CC_V) + { + fprintf (stream, "\t.variant_cc\t"); + assemble_name (stream, name); + fprintf (stream, "\n"); + } + } +} + +/* Implement ASM_DECLARE_FUNCTION_NAME. */ + +void +riscv_declare_function_name (FILE *stream, const char *name, tree fndecl) +{ + riscv_asm_output_variant_cc (stream, fndecl, name); + ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "function"); + ASM_OUTPUT_LABEL (stream, name); +} + +/* Implement ASM_OUTPUT_DEF_FROM_DECLS. */ + +void +riscv_asm_output_alias (FILE *stream, const tree decl, const tree target) +{ + const char *name = XSTR (XEXP (DECL_RTL (decl), 0), 0); + const char *value = IDENTIFIER_POINTER (target); + riscv_asm_output_variant_cc (stream, decl, name); + ASM_OUTPUT_DEF (stream, name, value); +} + +/* Implement ASM_OUTPUT_EXTERNAL. */ + +void +riscv_asm_output_external (FILE *stream, tree decl, const char *name) +{ + default_elf_asm_output_external (stream, decl, name); + riscv_asm_output_variant_cc (stream, decl, name); +} + /* Auxiliary function to emit RISC-V ELF attribute. */ static void riscv_emit_attribute () diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index b24b240dd75..1820593bab5 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -1021,6 +1021,21 @@ while (0) #define ASM_COMMENT_START "#" +/* Add output .variant_cc directive for specific function definition. */ +#undef ASM_DECLARE_FUNCTION_NAME +#define ASM_DECLARE_FUNCTION_NAME(STR, NAME, DECL) \ + riscv_declare_function_name (STR, NAME, DECL) + +/* Add output .variant_cc directive for specific alias definition. */ +#undef ASM_OUTPUT_DEF_FROM_DECLS +#define ASM_OUTPUT_DEF_FROM_DECLS(STR, DECL, TARGET) \ + riscv_asm_output_alias (STR, DECL, TARGET) + +/* Add output .variant_cc directive for specific extern function. */ +#undef ASM_OUTPUT_EXTERNAL +#define ASM_OUTPUT_EXTERNAL(STR, DECL, NAME) \ + riscv_asm_output_external (STR, DECL, NAME) + #undef SIZE_TYPE #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int") diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-variant_cc.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-variant_cc.c new file mode 100644 index 00000000000..4e45203f5b5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-variant_cc.c @@ -0,0 +1,39 @@ +/* { dg-do compile } */ +/* { dg-options "-O1 --param=riscv-vector-abi -Wno-psabi" } */ + +#include "riscv_vector.h" + +void +f_undef1 (vint8m1_t a); +void +f_undef2 (vint8m1x8_t a); +void +f_undef3 (vbool1_t a); +vint8m1_t +f_undef4 (); + +void +bar_real (vint8m1_t a, vint8m1x8_t b, vbool1_t c) +{ + f_undef1 (a); + f_undef2 (b); + f_undef3 (c); +} + +__attribute__ ((alias ("bar_real"))) void +bar_alias (vint8m1_t a, vint8m1x8_t b, vbool1_t c); + +void +f_1 (vint8m1_t *a, vint8m1x8_t *b, vbool1_t *c) +{ + bar_alias (*a, *b, *c); + *a = f_undef4 (); +} + +/* { dg-final { scan-assembler-times {\.variant_cc\tbar_real} 1 } } */ +/* { dg-final { scan-assembler-times {\.variant_cc\tbar_alias} 1 } } */ +/* { dg-final { scan-assembler-times {\.variant_cc\tf_1} 0 } } */ +/* { dg-final { scan-assembler-times {\.variant_cc\tf_undef1} 1 } } */ +/* { dg-final { scan-assembler-times {\.variant_cc\tf_undef2} 1 } } */ +/* { dg-final { scan-assembler-times {\.variant_cc\tf_undef3} 1 } } */ +/* { dg-final { scan-assembler-times {\.variant_cc\tf_undef4} 1 } } */ -- 2.36.3