From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by sourceware.org (Postfix) with ESMTPS id D9EBF3858D28 for ; Sun, 23 Jul 2023 13:54:26 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D9EBF3858D28 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1690120466; x=1721656466; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=1mziBZBYaKVtvUZq2F3MxqJ+ja8h5kX3dkp85/RxGhU=; b=mFuRnTZWgVQwncCOL9tdoU1/hKoxbPhQwDEB7nv0i2HXoApCmCGLQ9Yg tkY/IJpu5VZevybGK0tu6bMyvepIjKZO49iBDTC0V3z30iL/UPx/h3Yfv lf2m0dqCjq3JypmHEmT/VbrJU8CSxFy8a7yXxJzmH8R6WHXOLw7LtKU4V VwO94HRx78nqyLlnYKsL2bUtwx19ewy2yera9ThUi8qluSvuLFcpw335f IYwER5pZjMeNRKYhe6dAd73ch3uFAtDCT1pe8oMT6xu/9W2QC69JlT3ef 3RuefgVeoMSB2wPlknrvZgtPMCAr9TBEDvyrJcjExRBFXnzxZwRWCactw Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10780"; a="431076467" X-IronPort-AV: E=Sophos;i="6.01,226,1684825200"; d="scan'208";a="431076467" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jul 2023 06:54:24 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10780"; a="971967400" X-IronPort-AV: E=Sophos;i="6.01,226,1684825200"; d="scan'208";a="971967400" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by fmsmga006.fm.intel.com with ESMTP; 23 Jul 2023 06:54:22 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id 255FB10080C8; Sun, 23 Jul 2023 21:54:22 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Bugfix for allowing incorrect dyn for static rounding Date: Sun, 23 Jul 2023 21:54:21 +0800 Message-Id: <20230723135421.3723462-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Pan Li According to the spec, dyn rounding mode is invalid for RVV floating-point, this patch would like to fix this. Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv-vector-builtins-shapes.cc (struct alu_frm_def): Take range check. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-frm-error.c: Update cases. * gcc.target/riscv/rvv/base/float-point-frm-insert-6.c: Removed. --- .../riscv/riscv-vector-builtins-shapes.cc | 3 +- .../riscv/rvv/base/float-point-frm-error.c | 6 ++-- .../riscv/rvv/base/float-point-frm-insert-6.c | 33 ------------------- 3 files changed, 4 insertions(+), 38 deletions(-) delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.cc b/gcc/config/riscv/riscv-vector-builtins-shapes.cc index 69a67106418..22b5fe256df 100644 --- a/gcc/config/riscv/riscv-vector-builtins-shapes.cc +++ b/gcc/config/riscv/riscv-vector-builtins-shapes.cc @@ -285,8 +285,7 @@ struct alu_frm_def : public build_base { unsigned int frm_num = c.arg_num () - 2; - return c.require_immediate_range_or (frm_num, FRM_STATIC_MIN, - FRM_STATIC_MAX, FRM_DYN); + return c.require_immediate (frm_num, FRM_STATIC_MIN, FRM_STATIC_MAX); } return true; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-error.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-error.c index 4ebaa15ab0b..01d82d4e661 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-error.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-error.c @@ -7,9 +7,9 @@ typedef float float32_t; void test_float_point_frm_error (float32_t *out, vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) { - vfloat32m1_t v1 = __riscv_vfadd_vv_f32m1_rm (op1, op2, 5, vl); /* { dg-error {passing 5 to argument 3 of '__riscv_vfadd_vv_f32m1_rm', which expects a value in the range \[0, 4\] or 7} } */ - vfloat32m1_t v2 = __riscv_vfadd_vv_f32m1_rm (v1, v1, 6, vl); /* { dg-error {passing 6 to argument 3 of '__riscv_vfadd_vv_f32m1_rm', which expects a value in the range \[0, 4\] or 7} } */ - vfloat32m1_t v3 = __riscv_vfadd_vv_f32m1_rm (v2, v2, 8, vl); /* { dg-error {passing 8 to argument 3 of '__riscv_vfadd_vv_f32m1_rm', which expects a value in the range \[0, 4\] or 7} } */ + vfloat32m1_t v1 = __riscv_vfadd_vv_f32m1_rm (op1, op2, 5, vl); /* { dg-error {passing 5 to argument 3 of '__riscv_vfadd_vv_f32m1_rm', which expects a value in the range \[0, 4\]} } */ + vfloat32m1_t v2 = __riscv_vfadd_vv_f32m1_rm (v1, v1, 6, vl); /* { dg-error {passing 6 to argument 3 of '__riscv_vfadd_vv_f32m1_rm', which expects a value in the range \[0, 4\]} } */ + vfloat32m1_t v3 = __riscv_vfadd_vv_f32m1_rm (v2, v2, 8, vl); /* { dg-error {passing 8 to argument 3 of '__riscv_vfadd_vv_f32m1_rm', which expects a value in the range \[0, 4\]} } */ __riscv_vse32_v_f32m1 (out, v3, vl); } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c deleted file mode 100644 index 1ef0e015d8f..00000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c +++ /dev/null @@ -1,33 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ - -#include "riscv_vector.h" - -typedef float float32_t; - -vfloat32m1_t -test_riscv_vfadd_vv_f32m1_rm (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) { - return __riscv_vfadd_vv_f32m1_rm (op1, op2, 7, vl); -} - -vfloat32m1_t -test_vfadd_vv_f32m1_m_rm(vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2, - size_t vl) { - return __riscv_vfadd_vv_f32m1_m_rm(mask, op1, op2, 7, vl); -} - -vfloat32m1_t -test_vfadd_vf_f32m1_rm(vfloat32m1_t op1, float32_t op2, size_t vl) { - return __riscv_vfadd_vf_f32m1_rm(op1, op2, 7, vl); -} - -vfloat32m1_t -test_vfadd_vf_f32m1_m_rm(vbool32_t mask, vfloat32m1_t op1, float32_t op2, - size_t vl) { - return __riscv_vfadd_vf_f32m1_m_rm(mask, op1, op2, 7, vl); -} - -/* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 4 } } */ -/* { dg-final { scan-assembler-not {fsrm\s+[axs][0-9]+} } } */ -/* { dg-final { scan-assembler-not {frrm\s+[axs][0-9]+} } } */ -/* { dg-final { scan-assembler-not {fsrmi\s+[01234]} } } */ -- 2.34.1