From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pl1-x62b.google.com (mail-pl1-x62b.google.com [IPv6:2607:f8b0:4864:20::62b]) by sourceware.org (Postfix) with ESMTPS id 13BD9385840F for ; Tue, 25 Jul 2023 18:02:36 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 13BD9385840F Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-1bb7b8390e8so17317985ad.2 for ; Tue, 25 Jul 2023 11:02:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1690308155; x=1690912955; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UJwangr1qsERZVP3DcyizR0P7k+49zs4bpdVugIgS+Q=; b=1VbBvuiY6pbMGTNai04bMd0L1aaLPO9YfeqcFNIap+a+vXX8WxcAbI/u0Gqn5gAFO0 v2coquqlcWM+qPfJcEI8Xv9s+mKbZyN5paGJs6ZoddNU9CYShADBufO3VopVG/ba5d9Y oLoftQ3X2tdqdWhMnltu4eBitDzwCEF7fnTP+irwMeLVoixa76vc6r6yxTVvRgzoTmpA axZ0hINd1a1ivbC5Ue+NY4HBf8ykzfuh8OHkMpdCWrmZH2Gm21f8xdMRIF62gMoNZKAv WgZ7NcX2Ond6f5ji0EOg7wl0AhE0o89fp9tEVxUI3iaulluK26c44kCTkQ60EcdQH/+o k7tg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690308155; x=1690912955; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UJwangr1qsERZVP3DcyizR0P7k+49zs4bpdVugIgS+Q=; b=SsdprtTQkaiwY02xEraLWGi1HkhBDO14uLx/a1EdtIgZ1k96M7d3PoHyZCr2FQuXWl GSV2TiYcIZwkRV3MWouLxuvtAH+tTcjbST8sGOaOOuNDpKo0t6ENuCa8mLe07bvWsenj h0cEcH634Y0BnziG0W1dCPu2/h1RR9Pmc0nhnpG2HJES1TMfAujQpoZhmc0fgqcA09iF vyQr48IagW/8P6NCeH97s+a3cyHbBkXPS+IJzepH+rjjlNtdje5fXMB2uq59x4s5qCUp tFGA+lC9S9tMafYW1N2ktQkYkq/UtUusXbbjq61hwzgJnAwmHA4yIxutdcfAT7NFY2IU mzbg== X-Gm-Message-State: ABy/qLa1jZJYEPavfh757xeaOcXDtKd6Lc03ZgQ9LrPQfP7Dn0+fKINk eStIKrpJgNNFA8T9+ztn9TEAFwuWZJsBEKxUC9w= X-Google-Smtp-Source: APBJJlFsYfs004v2ddDxd4gv1Qj8d3siTTLXBV14t8YA5l/sd59wc6l6OnwYWYOl3SHSJRjIDiPIPQ== X-Received: by 2002:a17:902:d3c5:b0:1bb:a771:3542 with SMTP id w5-20020a170902d3c500b001bba7713542mr4401431plb.58.1690308154786; Tue, 25 Jul 2023 11:02:34 -0700 (PDT) Received: from patrick-ThinkPad-X1-Carbon-Gen-8.hq.rivosinc.com ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id p1-20020a1709028a8100b001b3ce619e2esm11283352plo.179.2023.07.25.11.02.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Jul 2023 11:02:34 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: jeffreyalaw@gmail.com, palmer@rivosinc.com, vineetg@rivosinc.com, andrew@sifive.com, kito.cheng@sifive.com, dlustig@nvidia.com, cmuellner@gcc.gnu.org, andrea@rivosinc.com, hboehm@google.com, Patrick O'Neill Subject: [gcc13 backport 09/12] RISC-V: Weaken mem_thread_fence Date: Tue, 25 Jul 2023 11:02:03 -0700 Message-Id: <20230725180206.284777-10-patrick@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230725180206.284777-1-patrick@rivosinc.com> References: <20230427162301.1151333-1-patrick@rivosinc.com> <20230725180206.284777-1-patrick@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This change brings atomic fences in line with table A.6 of the ISA manual. Relax mem_thread_fence according to the memmodel given. 2023-04-27 Patrick O'Neill gcc/ChangeLog: * config/riscv/sync.md (mem_thread_fence_1): Change fence depending on the given memory model. Signed-off-by: Patrick O'Neill --- gcc/config/riscv/sync.md | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index 3e6345e83a3..ba132d8a1ce 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -45,14 +45,24 @@ DONE; }) -;; Until the RISC-V memory model (hence its mapping from C++) is finalized, -;; conservatively emit a full FENCE. (define_insn "mem_thread_fence_1" [(set (match_operand:BLK 0 "" "") (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER)) (match_operand:SI 1 "const_int_operand" "")] ;; model "" - "fence\tiorw,iorw") + { + enum memmodel model = (enum memmodel) INTVAL (operands[1]); + model = memmodel_base (model); + if (model == MEMMODEL_SEQ_CST) + return "fence\trw,rw"; + else if (model == MEMMODEL_ACQ_REL) + return "fence.tso"; + else if (model == MEMMODEL_ACQUIRE) + return "fence\tr,rw"; + else if (model == MEMMODEL_RELEASE) + return "fence\trw,w"; + } + [(set (attr "length") (const_int 4))]) ;; Atomic memory operations. -- 2.34.1