From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pl1-x635.google.com (mail-pl1-x635.google.com [IPv6:2607:f8b0:4864:20::635]) by sourceware.org (Postfix) with ESMTPS id A59F4385AF98 for ; Tue, 25 Jul 2023 18:02:37 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A59F4385AF98 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pl1-x635.google.com with SMTP id d9443c01a7336-1b8ad8383faso44217235ad.0 for ; Tue, 25 Jul 2023 11:02:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1690308156; x=1690912956; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RRuZrOOs3faWx9Jun4Te3diKDc/iKDLt6SwONFdl680=; b=jPDd2CxLOkybDSKL4jXxEE/Ni8DerUaaX2XHCIGAL6agZqI2OXdDBAW8OJiMiCHTsd Y4dX/Li2Jgkn8tsHWMUTk3WcqltFJGcV71rql3Cc0Qx51daZWHPsyKOt/uJ6bRItIh2y /7Y2D/lVu2u0RXSqWgPiWSbv6PMiXAUXr4QvPJWkaiIdXeSzee37o8s2m0kfhcEcxBxq v5KuKhPtjqISudOs2Iv8qIsFq9KerLZYBj6s7Aqhq6oCQRO5wxorUuw0Ffbmkfv0kQhU Kq6pCqDG9CbjrCRkHnCYe2n49fv68hjzcgserzQ3VpKJ3QRmf32EjbIxqNGqXZy4Ikyw 4ZVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690308156; x=1690912956; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RRuZrOOs3faWx9Jun4Te3diKDc/iKDLt6SwONFdl680=; b=jonHQ5DXPrWNHzHRFfodmnBtDoE0W/V1FAEyAmqVzpdBaYuqEhHZ6c3PwnTsVfdma7 F5ndNozbk2wl1bgDCBkVse81I9FWWIShMFmU+iVvCOnO1W0KBv2jrAV1nOtUEqLAiQjG McDxVBrCIdxZEcBIoOs30trkOuCH0kIf6ZCCSUnd22UFo8qOFPbj7hlMdDgZMpO0zJmS LO0TZ/VkKbIvCS8HH7XeAfttMEgKng2YOU2bDYG8JAGwOU1ojSDmkXhPt8V8GyFKVyOn jsS43AFTZg09tUe4NXGwUCM1PLLqZxHZ0h5F4kRpQo/tn9YsUihBFax8OquMTzSBlXAT cojg== X-Gm-Message-State: ABy/qLYG/Vd9le5TxZqZ8mNQtsCd1RTRV2l+lWX7ggIVVjyv5IxlJCBS TFhe+1g3kr0edmPSmEG86M7r9oxGptFZGiLlO0Y= X-Google-Smtp-Source: APBJJlGrfVA2PfKK/RXvW0Htg2wL+5s7IKqc6oIu03gBpTCByNlxMJWntupUe1ZeMBCqBUHe/LLCow== X-Received: by 2002:a17:902:8607:b0:1b8:a31b:ac85 with SMTP id f7-20020a170902860700b001b8a31bac85mr17207plo.41.1690308156291; Tue, 25 Jul 2023 11:02:36 -0700 (PDT) Received: from patrick-ThinkPad-X1-Carbon-Gen-8.hq.rivosinc.com ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id p1-20020a1709028a8100b001b3ce619e2esm11283352plo.179.2023.07.25.11.02.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Jul 2023 11:02:35 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: jeffreyalaw@gmail.com, palmer@rivosinc.com, vineetg@rivosinc.com, andrew@sifive.com, kito.cheng@sifive.com, dlustig@nvidia.com, cmuellner@gcc.gnu.org, andrea@rivosinc.com, hboehm@google.com, Patrick O'Neill Subject: [gcc13 backport 10/12] RISC-V: Weaken atomic loads Date: Tue, 25 Jul 2023 11:02:04 -0700 Message-Id: <20230725180206.284777-11-patrick@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230725180206.284777-1-patrick@rivosinc.com> References: <20230427162301.1151333-1-patrick@rivosinc.com> <20230725180206.284777-1-patrick@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-13.2 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This change brings atomic loads in line with table A.6 of the ISA manual. 2023-04-27 Patrick O'Neill gcc/ChangeLog: * config/riscv/sync.md (atomic_load): Implement atomic load mapping. Signed-off-by: Patrick O'Neill --- gcc/config/riscv/sync.md | 28 ++++++++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index ba132d8a1ce..6e7c762ac57 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -26,6 +26,7 @@ UNSPEC_SYNC_OLD_OP_SUBWORD UNSPEC_SYNC_EXCHANGE UNSPEC_SYNC_EXCHANGE_SUBWORD + UNSPEC_ATOMIC_LOAD UNSPEC_ATOMIC_STORE UNSPEC_MEMORY_BARRIER ]) @@ -66,8 +67,31 @@ ;; Atomic memory operations. -;; Implement atomic stores with conservative fences. Fall back to fences for -;; atomic loads. +(define_insn "atomic_load" + [(set (match_operand:GPR 0 "register_operand" "=r") + (unspec_volatile:GPR + [(match_operand:GPR 1 "memory_operand" "A") + (match_operand:SI 2 "const_int_operand")] ;; model + UNSPEC_ATOMIC_LOAD))] + "TARGET_ATOMIC" + { + enum memmodel model = (enum memmodel) INTVAL (operands[2]); + model = memmodel_base (model); + + if (model == MEMMODEL_SEQ_CST) + return "fence\trw,rw\;" + "l\t%0,%1\;" + "fence\tr,rw"; + if (model == MEMMODEL_ACQUIRE) + return "l\t%0,%1\;" + "fence\tr,rw"; + else + return "l\t%0,%1"; + } + [(set_attr "type" "atomic") + (set (attr "length") (const_int 12))]) + +;; Implement atomic stores with conservative fences. ;; This allows us to be compatible with the ISA manual Table A.6 and Table A.7. (define_insn "atomic_store" [(set (match_operand:GPR 0 "memory_operand" "=A") -- 2.34.1