From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf1-x429.google.com (mail-pf1-x429.google.com [IPv6:2607:f8b0:4864:20::429]) by sourceware.org (Postfix) with ESMTPS id 68FEC385DC11 for ; Tue, 25 Jul 2023 18:02:31 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 68FEC385DC11 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pf1-x429.google.com with SMTP id d2e1a72fcca58-666e97fcc60so3414151b3a.3 for ; Tue, 25 Jul 2023 11:02:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1690308150; x=1690912950; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3N44+ius++qrlRw6UzNkGTIyvo46IXdY/Z/Z2aVapME=; b=A9+wSKvvHgk16KdqVvugv/Pjmm9qc+UzBBAZwQpRAGMdFFqpZ7Lc2r73K6BDCwSuNN PT4ZMbuwZyDS3uUWmqPk9y9icy1ovlzCmlhxEREXTJaZ6p3/Xt+AbxVkNSHwTCt/Opl+ YisyUy8JFk1rg4Qz4ODtm9kw866z6xebL+IPWRnhPq6NDtGMAw3xFWd6PgsPc4LeiUnS /YKTFx2dGCcl3iHYNSEhAND3fQQsK3wkGu34WSW76zaIV7gXnXg9eF77ZEgUMg878qN5 MNfbHAr6LmvwGggVMhFfUFyJXqKmVx5bA7LahCurw/E4JozLQ9RBrupr8Jthsk0vAHqN 6GQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690308150; x=1690912950; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3N44+ius++qrlRw6UzNkGTIyvo46IXdY/Z/Z2aVapME=; b=DmqT29nggHYK2bb4GlWP2xdP9Dp2WJUPcnXbJGREFNo8px46t2hxWcZPHlQD0jtocT KU7leMFpYasTZ+5D7RLZ2rW9rOziqQDmqcXkWwRcYFp3GVmi4FFilYxhrv9SE2J1OMPV qAyTtgJtoV3gPjG/rxyNW17X6mJzafDdRusAarqh3v+TmBBNDO4pfmLPTM1iLnaG1P9v MILAFShLRmywlp9UVwahwjQD+XGNEc9TA7IOzfvhA808CXbJUmiCo6ehEfy1HEaSd5Tb 2cBJKo5eutttzwtwwAEoCG3CQDX1LOX4ySE8oo8C6qlBWzmYZjxe2ztCHJKZELqz9LgB 3OXA== X-Gm-Message-State: ABy/qLaBORanDaJTsPbY7a+uCZoHZtxaYrXaRHo8fet5wWuPOtCtkcFD BgpeN81HJUOBFGuTAQdGueHv9txu/255OnbFC9I= X-Google-Smtp-Source: APBJJlGo9nAxTBCZOe73QwbyNYDpYZPnTb0wmyCkS/1t6Ev/OuVDvyjX9EA7sEscEH+H0QtkYNVxTg== X-Received: by 2002:a17:903:1c4:b0:1b8:72b2:fd3b with SMTP id e4-20020a17090301c400b001b872b2fd3bmr11163395plh.54.1690308150205; Tue, 25 Jul 2023 11:02:30 -0700 (PDT) Received: from patrick-ThinkPad-X1-Carbon-Gen-8.hq.rivosinc.com ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id p1-20020a1709028a8100b001b3ce619e2esm11283352plo.179.2023.07.25.11.02.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Jul 2023 11:02:29 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: jeffreyalaw@gmail.com, palmer@rivosinc.com, vineetg@rivosinc.com, andrew@sifive.com, kito.cheng@sifive.com, dlustig@nvidia.com, cmuellner@gcc.gnu.org, andrea@rivosinc.com, hboehm@google.com, Patrick O'Neill Subject: [gcc13 backport 05/12] RISC-V: Add AMO release bits Date: Tue, 25 Jul 2023 11:01:59 -0700 Message-Id: <20230725180206.284777-6-patrick@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230725180206.284777-1-patrick@rivosinc.com> References: <20230427162301.1151333-1-patrick@rivosinc.com> <20230725180206.284777-1-patrick@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-13.2 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This patch sets the relevant .rl bits on amo operations. 2023-04-27 Patrick O'Neill gcc/ChangeLog: * config/riscv/riscv.cc (riscv_print_operand): Change behavior of %A to include release bits. Signed-off-by: Patrick O'Neill --- gcc/config/riscv/riscv.cc | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 11b897aca5c..df55c427b1b 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -4498,8 +4498,13 @@ riscv_print_operand (FILE *file, rtx op, int letter) break; case 'A': - if (riscv_memmodel_needs_amo_acquire (model)) + if (riscv_memmodel_needs_amo_acquire (model) + && riscv_memmodel_needs_release_fence (model)) + fputs (".aqrl", file); + else if (riscv_memmodel_needs_amo_acquire (model)) fputs (".aq", file); + else if (riscv_memmodel_needs_release_fence (model)) + fputs (".rl", file); break; case 'F': -- 2.34.1