From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pl1-x631.google.com (mail-pl1-x631.google.com [IPv6:2607:f8b0:4864:20::631]) by sourceware.org (Postfix) with ESMTPS id 09CF93851145 for ; Tue, 25 Jul 2023 18:02:34 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 09CF93851145 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-1b890e2b9b7so30244385ad.3 for ; Tue, 25 Jul 2023 11:02:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1690308152; x=1690912952; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+an3mJhALM0mRGewGvKmtbG0iArBIsdEVXHkmgkog/s=; b=z1v8t/NX1N0nlKT/mBb6hycLtyray0kDCWrJL7EoDA6ZWbetWJQazJu0ATyoeR56aG o8RXSGbWOCRQP/Likz3Tp2LcmdCqzXnUj7760+Sg00D7wKuglSKwjvfzpLI1EwF/cCks mgL7mLXgqGLJl6XZwZ/m1ADW+B2jSmhxIQo9LX/wOm0Z6/2ii/XTXln+mm0P6+ee0GLk 3UlT4vb/343xNqp4z5JedaWjuV+8xto8MFj0HtDKuDpWfSM3N/1SAq/HpprzYiROXUgh WIOolYb9L8+GqL9YiyE2x5SotDjy9fa23HjUJ4HVPTdE0lYrPIHX3pC1WSprq8NBcyTw UCVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690308152; x=1690912952; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+an3mJhALM0mRGewGvKmtbG0iArBIsdEVXHkmgkog/s=; b=H+zWSyxO3oGSjEJ2GYZGZyZRyRAxM2PQ7GXhnH099Lg9Tmlnjz08Kihp7+CWCgvkNT my7jjBhYHRSMRifB1fO4U0v4rW4b4UAmeIAOPiUG5O4rT5Z4pU1IGfPFFyyrpCF2L60c Hsa+KyW9Ad5ulTc8mRBcT029vOVnzs7C88raV3Zk7ABVT0wbMSDDIzEfwhAQmudkwu5H PCxMjqHlYDAFhP+0SWHJOIV7fYxepXgV+/BhfUbf+NGS5Gj7If4z2yKA4Hnv06uXEqmr R6Rb71Y/n0XzFUhpt00rmMxdzYOfra+3szbDmhhNUSuPEvLt+ZrNF5cx2kc0TFsKpkRu VS0g== X-Gm-Message-State: ABy/qLaNtj5Mt0fzBgnrAnVT2vyV7TdNvllD5CIwqqoAutuzoEKIIpVD xq3s7LovA4Hncg8BVmkYhiqBhv1NwTNJgDqAzkU= X-Google-Smtp-Source: APBJJlEFnNdq3tiaDNYXD2Hy6nPiQQfvALEBvZTlI0nBOWYvPaulYe1YP3mpkuTHrK+zBEPB2W/GJA== X-Received: by 2002:a17:902:d4ce:b0:1b8:4e69:c8f7 with SMTP id o14-20020a170902d4ce00b001b84e69c8f7mr22455plg.23.1690308152402; Tue, 25 Jul 2023 11:02:32 -0700 (PDT) Received: from patrick-ThinkPad-X1-Carbon-Gen-8.hq.rivosinc.com ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id p1-20020a1709028a8100b001b3ce619e2esm11283352plo.179.2023.07.25.11.02.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Jul 2023 11:02:32 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: jeffreyalaw@gmail.com, palmer@rivosinc.com, vineetg@rivosinc.com, andrew@sifive.com, kito.cheng@sifive.com, dlustig@nvidia.com, cmuellner@gcc.gnu.org, andrea@rivosinc.com, hboehm@google.com, Patrick O'Neill Subject: [gcc13 backport 07/12] RISC-V: Eliminate AMO op fences Date: Tue, 25 Jul 2023 11:02:01 -0700 Message-Id: <20230725180206.284777-8-patrick@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230725180206.284777-1-patrick@rivosinc.com> References: <20230427162301.1151333-1-patrick@rivosinc.com> <20230725180206.284777-1-patrick@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Atomic operations with the appropriate bits set already enfore release semantics. Remove unnecessary release fences from atomic ops. This change brings AMO ops in line with table A.6 of the ISA manual. 2023-04-27 Patrick O'Neill gcc/ChangeLog: * config/riscv/riscv.cc (riscv_memmodel_needs_amo_release): Change function name. (riscv_print_operand): Remove unneeded %F case. * config/riscv/sync.md: Remove unneeded fences. Signed-off-by: Patrick O'Neill --- gcc/config/riscv/riscv.cc | 16 +++++----------- gcc/config/riscv/sync.md | 12 ++++++------ 2 files changed, 11 insertions(+), 17 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index df55c427b1b..951f6b5cf42 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -4307,11 +4307,11 @@ riscv_memmodel_needs_amo_acquire (enum memmodel model) } } -/* Return true if a FENCE should be emitted to before a memory access to - implement the release portion of memory model MODEL. */ +/* Return true if the .RL suffix should be added to an AMO to implement the + release portion of memory model MODEL. */ static bool -riscv_memmodel_needs_release_fence (enum memmodel model) +riscv_memmodel_needs_amo_release (enum memmodel model) { switch (model) { @@ -4337,7 +4337,6 @@ riscv_memmodel_needs_release_fence (enum memmodel model) 'R' Print the low-part relocation associated with OP. 'C' Print the integer branch condition for comparison OP. 'A' Print the atomic operation suffix for memory model OP. - 'F' Print a FENCE if the memory model requires a release. 'z' Print x0 if OP is zero, otherwise print OP normally. 'i' Print i if the operand is not a register. 'S' Print shift-index of single-bit mask OP. @@ -4499,19 +4498,14 @@ riscv_print_operand (FILE *file, rtx op, int letter) case 'A': if (riscv_memmodel_needs_amo_acquire (model) - && riscv_memmodel_needs_release_fence (model)) + && riscv_memmodel_needs_amo_release (model)) fputs (".aqrl", file); else if (riscv_memmodel_needs_amo_acquire (model)) fputs (".aq", file); - else if (riscv_memmodel_needs_release_fence (model)) + else if (riscv_memmodel_needs_amo_release (model)) fputs (".rl", file); break; - case 'F': - if (riscv_memmodel_needs_release_fence (model)) - fputs ("fence iorw,ow; ", file); - break; - case 'i': if (code != REG) fputs ("i", file); diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index 1acb78a9ae4..9a3b57bd09f 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -91,9 +91,9 @@ (match_operand:SI 2 "const_int_operand")] ;; model UNSPEC_SYNC_OLD_OP))] "TARGET_ATOMIC" - "%F2amo.%A2 zero,%z1,%0" + "amo.%A2\tzero,%z1,%0" [(set_attr "type" "atomic") - (set (attr "length") (const_int 8))]) + (set (attr "length") (const_int 4))]) (define_insn "atomic_fetch_" [(set (match_operand:GPR 0 "register_operand" "=&r") @@ -105,9 +105,9 @@ (match_operand:SI 3 "const_int_operand")] ;; model UNSPEC_SYNC_OLD_OP))] "TARGET_ATOMIC" - "%F3amo.%A3 %0,%z2,%1" + "amo.%A3\t%0,%z2,%1" [(set_attr "type" "atomic") - (set (attr "length") (const_int 8))]) + (set (attr "length") (const_int 4))]) (define_insn "subword_atomic_fetch_strong_" [(set (match_operand:SI 0 "register_operand" "=&r") ;; old value at mem @@ -247,9 +247,9 @@ (set (match_dup 1) (match_operand:GPR 2 "register_operand" "0"))] "TARGET_ATOMIC" - "%F3amoswap.%A3 %0,%z2,%1" + "amoswap.%A3\t%0,%z2,%1" [(set_attr "type" "atomic") - (set (attr "length") (const_int 8))]) + (set (attr "length") (const_int 4))]) (define_expand "atomic_exchange" [(match_operand:SHORT 0 "register_operand") ;; old value at mem -- 2.34.1