From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mgamail.intel.com (unknown [192.55.52.43]) by sourceware.org (Postfix) with ESMTPS id CB4353858C2F for ; Thu, 27 Jul 2023 10:44:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org CB4353858C2F Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1690454668; x=1721990668; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=YOVscn2HFpJqiwAnvcrwpI0WWm8JS2o18l+8vYaH1u8=; b=dOLYxLduhEQ5ljzme04uHJ71YP3BZFIFroO2j7mRq8+WDE13RKDb//W/ CdLXqoZFSnP7JnYBPSmGeMPCQtF/FB1r9fGhAgPBauPYqdYhafEaj7oFs Wp60d5XuPFtsRk7l4dsGL+xzvjwrugQfBJAKGZx+GLucKqydoxGiibB9S cS5TOPmmfM+c7Z/NoHWyz1BE9TWRrH09Rb8DeBKbrRsHCyL7pGq7jV930 /CsbcTzdxg0c0xlTiZDTqaB7crBxOsIS4zd9EEbN8DO//CRcXtNHTkPRK BF6jSU4gA9F3gifT74TPX2Z9NezV+KDl/Gd+rU0880r3CGRBtmZrUUGvj A==; X-IronPort-AV: E=McAfee;i="6600,9927,10783"; a="454642192" X-IronPort-AV: E=Sophos;i="6.01,234,1684825200"; d="scan'208";a="454642192" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2023 03:44:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10783"; a="762123766" X-IronPort-AV: E=Sophos;i="6.01,234,1684825200"; d="scan'208";a="762123766" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by orsmga001.jf.intel.com with ESMTP; 27 Jul 2023 03:44:02 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id ADA141006F14; Thu, 27 Jul 2023 18:44:01 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Remove unnecessary vread_csr/vwrite_csr intrinsic. Date: Thu, 27 Jul 2023 18:43:53 +0800 Message-Id: <20230727104353.3890397-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Pan Li According to below RVV doc, the related intrinsic is not longer needed. https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/249 Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv_vector.h (enum RVV_CSR): Removed. (vread_csr): Ditto. (vwrite_csr): Ditto. --- gcc/config/riscv/riscv_vector.h | 51 --------------------------------- 1 file changed, 51 deletions(-) diff --git a/gcc/config/riscv/riscv_vector.h b/gcc/config/riscv/riscv_vector.h index ff54b6be863..3366fd972b5 100644 --- a/gcc/config/riscv/riscv_vector.h +++ b/gcc/config/riscv/riscv_vector.h @@ -35,57 +35,6 @@ extern "C" { #endif -enum RVV_CSR { - RVV_VSTART = 0, - RVV_VXSAT, - RVV_VXRM, - RVV_VCSR, -}; - -__extension__ extern __inline unsigned long -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vread_csr(enum RVV_CSR csr) -{ - unsigned long rv = 0; - switch (csr) - { - case RVV_VSTART: - __asm__ __volatile__ ("csrr\t%0,vstart" : "=r"(rv) : : "memory"); - break; - case RVV_VXSAT: - __asm__ __volatile__ ("csrr\t%0,vxsat" : "=r"(rv) : : "memory"); - break; - case RVV_VXRM: - __asm__ __volatile__ ("csrr\t%0,vxrm" : "=r"(rv) : : "memory"); - break; - case RVV_VCSR: - __asm__ __volatile__ ("csrr\t%0,vcsr" : "=r"(rv) : : "memory"); - break; - } - return rv; -} - -__extension__ extern __inline void -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vwrite_csr(enum RVV_CSR csr, unsigned long value) -{ - switch (csr) - { - case RVV_VSTART: - __asm__ __volatile__ ("csrw\tvstart,%z0" : : "rJ"(value) : "memory"); - break; - case RVV_VXSAT: - __asm__ __volatile__ ("csrw\tvxsat,%z0" : : "rJ"(value) : "memory"); - break; - case RVV_VXRM: - __asm__ __volatile__ ("csrw\tvxrm,%z0" : : "rJ"(value) : "memory"); - break; - case RVV_VCSR: - __asm__ __volatile__ ("csrw\tvcsr,%z0" : : "rJ"(value) : "memory"); - break; - } -} - /* NOTE: This implementation of riscv_vector.h is intentionally short. It does not define the RVV types and intrinsic functions directly in C and C++ code, but instead uses the following pragma to tell GCC to insert the -- 2.34.1