From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mgamail.intel.com (unknown [134.134.136.100]) by sourceware.org (Postfix) with ESMTPS id 288D63858412 for ; Mon, 31 Jul 2023 02:56:52 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 288D63858412 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1690772212; x=1722308212; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=F+Te+ofPsWPj073U0CKUqszyzetfHKX+2hpgaTkZ9v8=; b=a0iBAQiI0HkK7+7OXMtN5pfPNTZfhQJmcE69bNrVcxG94wAxKBV/s4T3 uxJyr31Jxxai6ZeAH3zzxVlYivgABbOzuNSmzqepqj84JP95ateuwl/Am f4UcXAWa/FAgBfZeSFXj7aiZBPh+zLBGPrfEVhc/E4N0V19LRV0XFk5wk EgRWdIWZU9Q3MZnwJ03gQmo3V5wvCtqvNuDbabOgWvq11Uj/2sVye76MJ 5Og65/oFSu0LcTZaNSzK72/dU03emWjCET6OJjmjll5qxYYeOOtMDcVPm tltTOz/4Q301h4s3qKTyVrr4S9+kh4HIDep7YVHQoDUcMo4zycSL7VOny w==; X-IronPort-AV: E=McAfee;i="6600,9927,10787"; a="435205736" X-IronPort-AV: E=Sophos;i="6.01,243,1684825200"; d="scan'208";a="435205736" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jul 2023 19:56:51 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10787"; a="731426467" X-IronPort-AV: E=Sophos;i="6.01,243,1684825200"; d="scan'208";a="731426467" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by fmsmga007.fm.intel.com with ESMTP; 30 Jul 2023 19:56:49 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id 7E9091006F38; Mon, 31 Jul 2023 10:56:48 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@sifive.com, pan2.li@intel.com, yanzhang.wang@intel.com Subject: [PATCH v1] RISC-V: Bugfix for RVV floating-point rm suffix sequence Date: Mon, 31 Jul 2023 10:56:46 +0800 Message-Id: <20230731025646.1021646-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Pan Li According to below RVV intrinsic doc, the RVV floating-point intrinsic name with rounding mode should be: _rm_m instead of: _m_rm https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/226 This patch fix this naming sequence issue and adjust the test cases. Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv-vector-builtins-shapes.cc (struct alu_frm_def): Move rm suffix before mask. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-frm-insert-1.c: Adjust test cases. * gcc.target/riscv/rvv/base/float-point-frm.c: Ditto. --- gcc/config/riscv/riscv-vector-builtins-shapes.cc | 10 +++++----- .../riscv/rvv/base/float-point-frm-insert-1.c | 14 +++++++------- .../gcc.target/riscv/rvv/base/float-point-frm.c | 16 ++++++++-------- 3 files changed, 20 insertions(+), 20 deletions(-) diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.cc b/gcc/config/riscv/riscv-vector-builtins-shapes.cc index 22b5fe256df..6af57c22bfb 100644 --- a/gcc/config/riscv/riscv-vector-builtins-shapes.cc +++ b/gcc/config/riscv/riscv-vector-builtins-shapes.cc @@ -261,6 +261,11 @@ struct alu_frm_def : public build_base b.append_name (type_suffixes[instance.type.index].vector); } + /* According to rvv-intrinsic-doc, it does not add "_rm" suffix + for vop_rm C++ overloaded API. */ + if (!overloaded_p) + b.append_name ("_rm"); + /* According to rvv-intrinsic-doc, it does not add "_m" suffix for vop_m C++ overloaded API. */ if (overloaded_p && instance.pred == PRED_TYPE_m) @@ -268,11 +273,6 @@ struct alu_frm_def : public build_base b.append_name (predication_suffixes[instance.pred]); - /* According to rvv-intrinsic-doc, it does not add "_rm" suffix - for vop_rm C++ overloaded API. */ - if (!overloaded_p) - b.append_name ("_rm"); - return b.finish_name (); } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-1.c index 608b3883dd0..d6c5e1bddd6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-1.c @@ -11,20 +11,20 @@ test_riscv_vfadd_vv_f32m1_rm (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) { } vfloat32m1_t -test_vfadd_vv_f32m1_m_rm(vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2, +test_vfadd_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) { - return __riscv_vfadd_vv_f32m1_m_rm(mask, op1, op2, 1, vl); + return __riscv_vfadd_vv_f32m1_rm_m (mask, op1, op2, 1, vl); } vfloat32m1_t -test_vfadd_vf_f32m1_rm(vfloat32m1_t op1, float32_t op2, size_t vl) { - return __riscv_vfadd_vf_f32m1_rm(op1, op2, 2, vl); +test_vfadd_vf_f32m1_rm (vfloat32m1_t op1, float32_t op2, size_t vl) { + return __riscv_vfadd_vf_f32m1_rm (op1, op2, 2, vl); } vfloat32m1_t -test_vfadd_vf_f32m1_m_rm(vbool32_t mask, vfloat32m1_t op1, float32_t op2, - size_t vl) { - return __riscv_vfadd_vf_f32m1_m_rm(mask, op1, op2, 3, vl); +test_vfadd_vf_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, float32_t op2, + size_t vl) { + return __riscv_vfadd_vf_f32m1_rm_m (mask, op1, op2, 3, vl); } /* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm.c index 95271b2c822..1f142605cc3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm.c @@ -11,20 +11,20 @@ test_riscv_vfadd_vv_f32m1_rm (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) { } vfloat32m1_t -test_vfadd_vv_f32m1_m_rm(vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2, - size_t vl) { - return __riscv_vfadd_vv_f32m1_m_rm(mask, op1, op2, 0, vl); +test_vfadd_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2, + size_t vl) { + return __riscv_vfadd_vv_f32m1_rm_m (mask, op1, op2, 0, vl); } vfloat32m1_t -test_vfadd_vf_f32m1_rm(vfloat32m1_t op1, float32_t op2, size_t vl) { - return __riscv_vfadd_vf_f32m1_rm(op1, op2, 0, vl); +test_vfadd_vf_f32m1_rm (vfloat32m1_t op1, float32_t op2, size_t vl) { + return __riscv_vfadd_vf_f32m1_rm (op1, op2, 0, vl); } vfloat32m1_t -test_vfadd_vf_f32m1_m_rm(vbool32_t mask, vfloat32m1_t op1, float32_t op2, - size_t vl) { - return __riscv_vfadd_vf_f32m1_m_rm(mask, op1, op2, 0, vl); +test_vfadd_vf_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, float32_t op2, + size_t vl) { + return __riscv_vfadd_vf_f32m1_rm_m (mask, op1, op2, 0, vl); } /* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 4 } } */ -- 2.34.1