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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id d7-20020aa78147000000b0068718aadda7sm3813932pfn.108.2023.07.30.23.52.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Jul 2023 23:52:58 -0700 (PDT) From: Kito Cheng To: gcc-patches@gcc.gnu.org, kito.cheng@gmail.com, juzhe.zhong@rivai.ai, rdapp.gcc@gmail.com, pan2.li@intel.com Cc: Kito Cheng Subject: [PATCH] RISC-V: Return machine_mode rather than opt_machine_mode for get_mask_mode, NFC Date: Mon, 31 Jul 2023 14:52:28 +0800 Message-Id: <20230731065228.69779-1-kito.cheng@sifive.com> X-Mailer: git-send-email 2.40.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: We always want get_mask_mode return a valid mode, it's something wrong if it failed, so I think we could just move the `.require ()` into get_mask_mode, instead of calling that every call-site. The only exception is riscv_get_mask_mode, it might put supported mode into get_mask_mode, so added a check with riscv_v_ext_mode_p to make sure only valid vector mode will ask get_mask_mode. gcc/ChangeLog: * config/riscv/autovec.md (abs2): Remove `.require ()`. * config/riscv/riscv-protos.h (get_mask_mode): Update return type. * config/riscv/riscv-v.cc (rvv_builder::rvv_builder): Remove `.require ()`. (emit_vlmax_insn): Ditto. (emit_vlmax_fp_insn): Ditto. (emit_vlmax_ternary_insn): Ditto. (emit_vlmax_fp_ternary_insn): Ditto. (emit_nonvlmax_fp_ternary_tu_insn): Ditto. (emit_nonvlmax_insn): Ditto. (emit_vlmax_slide_insn): Ditto. (emit_nonvlmax_slide_tu_insn): Ditto. (emit_vlmax_merge_insn): Ditto. (emit_vlmax_masked_insn): Ditto. (emit_nonvlmax_masked_insn): Ditto. (emit_vlmax_masked_store_insn): Ditto. (emit_nonvlmax_masked_store_insn): Ditto. (emit_vlmax_masked_mu_insn): Ditto. (emit_nonvlmax_tu_insn): Ditto. (emit_nonvlmax_fp_tu_insn): Ditto. (emit_scalar_move_insn): Ditto. (emit_vlmax_compress_insn): Ditto. (emit_vlmax_reduction_insn): Ditto. (emit_vlmax_fp_reduction_insn): Ditto. (emit_nonvlmax_fp_reduction_insn): Ditto. (expand_vec_series): Ditto. (expand_vector_init_merge_repeating_sequence): Ditto. (expand_vec_perm): Ditto. (shuffle_merge_patterns): Ditto. (shuffle_compress_patterns): Ditto. (shuffle_decompress_patterns): Ditto. (expand_reduction): Ditto. (get_mask_mode): Update return type. * config/riscv/riscv.cc (riscv_get_mask_mode): Check vector type is valid, and use new get_mask_mode interface. --- gcc/config/riscv/autovec.md | 2 +- gcc/config/riscv/riscv-protos.h | 2 +- gcc/config/riscv/riscv-v.cc | 68 ++++++++++++++++----------------- gcc/config/riscv/riscv.cc | 5 +-- 4 files changed, 37 insertions(+), 40 deletions(-) diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index b7ea3101f5a..fd7ec911e87 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -912,7 +912,7 @@ (define_expand "abs2" "TARGET_VECTOR" { rtx zero = gen_const_vec_duplicate (mode, GEN_INT (0)); - machine_mode mask_mode = riscv_vector::get_mask_mode (mode).require (); + machine_mode mask_mode = riscv_vector::get_mask_mode (mode); rtx mask = gen_reg_rtx (mask_mode); riscv_vector::expand_vec_cmp (mask, LT, operands[1], zero); diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 7d8bf2b81f8..324991e2619 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -312,7 +312,7 @@ bool slide1_sew64_helper (int, machine_mode, machine_mode, rtx gen_avl_for_scalar_move (rtx); void expand_tuple_move (rtx *); machine_mode preferred_simd_mode (scalar_mode); -opt_machine_mode get_mask_mode (machine_mode); +machine_mode get_mask_mode (machine_mode); void expand_vec_series (rtx, rtx, rtx); void expand_vec_init (rtx, rtx); void expand_vec_perm (rtx, rtx, rtx, rtx); diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 0a355eb3c7a..5ab749f4343 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -285,7 +285,7 @@ public: m_inner_mode = GET_MODE_INNER (mode); m_inner_bits_size = GET_MODE_BITSIZE (m_inner_mode); m_inner_bytes_size = GET_MODE_SIZE (m_inner_mode); - m_mask_mode = get_mask_mode (mode).require (); + m_mask_mode = get_mask_mode (mode); gcc_assert ( int_mode_for_size (inner_bits_size (), 0).exists (&m_inner_int_mode)); @@ -676,7 +676,7 @@ void emit_vlmax_insn (unsigned icode, int op_num, rtx *ops, rtx vl) { machine_mode dest_mode = GET_MODE (ops[0]); - machine_mode mask_mode = get_mask_mode (dest_mode).require (); + machine_mode mask_mode = get_mask_mode (dest_mode); insn_expander e (op_num, /* HAS_DEST_P */ true, /* FULLY_UNMASKED_P */ true, @@ -698,7 +698,7 @@ void emit_vlmax_fp_insn (unsigned icode, int op_num, rtx *ops, rtx vl) { machine_mode dest_mode = GET_MODE (ops[0]); - machine_mode mask_mode = get_mask_mode (dest_mode).require (); + machine_mode mask_mode = get_mask_mode (dest_mode); insn_expander e (op_num, /* HAS_DEST_P */ true, /* FULLY_UNMASKED_P */ true, @@ -721,7 +721,7 @@ void emit_vlmax_ternary_insn (unsigned icode, int op_num, rtx *ops, rtx vl) { machine_mode dest_mode = GET_MODE (ops[0]); - machine_mode mask_mode = get_mask_mode (dest_mode).require (); + machine_mode mask_mode = get_mask_mode (dest_mode); insn_expander e (/*OP_NUM*/ op_num, /*HAS_DEST_P*/ true, /*FULLY_UNMASKED_P*/ true, @@ -742,7 +742,7 @@ void emit_vlmax_fp_ternary_insn (unsigned icode, int op_num, rtx *ops, rtx vl) { machine_mode dest_mode = GET_MODE (ops[0]); - machine_mode mask_mode = get_mask_mode (dest_mode).require (); + machine_mode mask_mode = get_mask_mode (dest_mode); insn_expander e (/*OP_NUM*/ op_num, /*HAS_DEST_P*/ true, /*FULLY_UNMASKED_P*/ true, @@ -764,7 +764,7 @@ static void emit_nonvlmax_fp_ternary_tu_insn (unsigned icode, int op_num, rtx *ops, rtx vl) { machine_mode dest_mode = GET_MODE (ops[0]); - machine_mode mask_mode = get_mask_mode (dest_mode).require (); + machine_mode mask_mode = get_mask_mode (dest_mode); insn_expander e (/*OP_NUM*/ op_num, /*HAS_DEST_P*/ true, /*FULLY_UNMASKED_P*/ false, @@ -786,7 +786,7 @@ void emit_nonvlmax_insn (unsigned icode, int op_num, rtx *ops, rtx avl) { machine_mode dest_mode = GET_MODE (ops[0]); - machine_mode mask_mode = get_mask_mode (dest_mode).require (); + machine_mode mask_mode = get_mask_mode (dest_mode); insn_expander e (op_num, /* HAS_DEST_P */ true, /* FULLY_UNMASKED_P */ true, @@ -808,7 +808,7 @@ void emit_vlmax_slide_insn (unsigned icode, rtx *ops) { machine_mode dest_mode = GET_MODE (ops[0]); - machine_mode mask_mode = get_mask_mode (dest_mode).require (); + machine_mode mask_mode = get_mask_mode (dest_mode); insn_expander e (RVV_SLIDE_OP, /* HAS_DEST_P */ true, /* FULLY_UNMASKED_P */ true, @@ -830,7 +830,7 @@ void emit_nonvlmax_slide_tu_insn (unsigned icode, rtx *ops, rtx avl) { machine_mode dest_mode = GET_MODE (ops[0]); - machine_mode mask_mode = get_mask_mode (dest_mode).require (); + machine_mode mask_mode = get_mask_mode (dest_mode); insn_expander e (RVV_SLIDE_OP, /* HAS_DEST_P */ true, /* FULLY_UNMASKED_P */ true, @@ -853,7 +853,7 @@ void emit_vlmax_merge_insn (unsigned icode, int op_num, rtx *ops) { machine_mode dest_mode = GET_MODE (ops[0]); - machine_mode mask_mode = get_mask_mode (dest_mode).require (); + machine_mode mask_mode = get_mask_mode (dest_mode); insn_expander e (op_num, /* HAS_DEST_P */ true, /* FULLY_UNMASKED_P */ false, @@ -908,7 +908,7 @@ static void emit_vlmax_masked_insn (unsigned icode, int op_num, rtx *ops) { machine_mode dest_mode = GET_MODE (ops[0]); - machine_mode mask_mode = get_mask_mode (dest_mode).require (); + machine_mode mask_mode = get_mask_mode (dest_mode); insn_expander e (/*OP_NUM*/ op_num, /*HAS_DEST_P*/ true, /*FULLY_UNMASKED_P*/ false, @@ -926,7 +926,7 @@ static void emit_nonvlmax_masked_insn (unsigned icode, int op_num, rtx *ops, rtx avl) { machine_mode dest_mode = GET_MODE (ops[0]); - machine_mode mask_mode = get_mask_mode (dest_mode).require (); + machine_mode mask_mode = get_mask_mode (dest_mode); insn_expander e (/*OP_NUM*/ op_num, /*HAS_DEST_P*/ true, /*FULLY_UNMASKED_P*/ false, @@ -945,7 +945,7 @@ static void emit_vlmax_masked_store_insn (unsigned icode, int op_num, rtx *ops) { machine_mode dest_mode = GET_MODE (ops[0]); - machine_mode mask_mode = get_mask_mode (dest_mode).require (); + machine_mode mask_mode = get_mask_mode (dest_mode); insn_expander e (/*OP_NUM*/ op_num, /*HAS_DEST_P*/ false, /*FULLY_UNMASKED_P*/ false, @@ -961,7 +961,7 @@ static void emit_nonvlmax_masked_store_insn (unsigned icode, int op_num, rtx *ops, rtx avl) { machine_mode dest_mode = GET_MODE (ops[0]); - machine_mode mask_mode = get_mask_mode (dest_mode).require (); + machine_mode mask_mode = get_mask_mode (dest_mode); insn_expander e (/*OP_NUM*/ op_num, /*HAS_DEST_P*/ false, /*FULLY_UNMASKED_P*/ false, @@ -978,7 +978,7 @@ void emit_vlmax_masked_mu_insn (unsigned icode, int op_num, rtx *ops) { machine_mode dest_mode = GET_MODE (ops[0]); - machine_mode mask_mode = get_mask_mode (dest_mode).require (); + machine_mode mask_mode = get_mask_mode (dest_mode); insn_expander e (/*OP_NUM*/ op_num, /*HAS_DEST_P*/ true, /*FULLY_UNMASKED_P*/ false, @@ -996,7 +996,7 @@ static void emit_nonvlmax_tu_insn (unsigned icode, int op_num, rtx *ops, rtx avl) { machine_mode dest_mode = GET_MODE (ops[0]); - machine_mode mask_mode = get_mask_mode (dest_mode).require (); + machine_mode mask_mode = get_mask_mode (dest_mode); insn_expander e (/*OP_NUM*/ op_num, /*HAS_DEST_P*/ true, /*FULLY_UNMASKED_P*/ false, @@ -1015,7 +1015,7 @@ static void emit_nonvlmax_fp_tu_insn (unsigned icode, int op_num, rtx *ops, rtx avl) { machine_mode dest_mode = GET_MODE (ops[0]); - machine_mode mask_mode = get_mask_mode (dest_mode).require (); + machine_mode mask_mode = get_mask_mode (dest_mode); insn_expander e (/*OP_NUM*/ op_num, /*HAS_DEST_P*/ true, /*FULLY_UNMASKED_P*/ false, @@ -1036,7 +1036,7 @@ void emit_scalar_move_insn (unsigned icode, rtx *ops, rtx len) { machine_mode dest_mode = GET_MODE (ops[0]); - machine_mode mask_mode = get_mask_mode (dest_mode).require (); + machine_mode mask_mode = get_mask_mode (dest_mode); insn_expander e (RVV_SCALAR_MOV_OP, /* HAS_DEST_P */ true, /* FULLY_UNMASKED_P */ false, @@ -1156,7 +1156,7 @@ static void emit_vlmax_compress_insn (unsigned icode, rtx *ops) { machine_mode dest_mode = GET_MODE (ops[0]); - machine_mode mask_mode = get_mask_mode (dest_mode).require (); + machine_mode mask_mode = get_mask_mode (dest_mode); insn_expander e (RVV_COMPRESS_OP, /* HAS_DEST_P */ true, /* FULLY_UNMASKED_P */ false, @@ -1174,7 +1174,7 @@ static void emit_vlmax_reduction_insn (unsigned icode, int op_num, rtx *ops) { machine_mode dest_mode = GET_MODE (ops[0]); - machine_mode mask_mode = get_mask_mode (GET_MODE (ops[1])).require (); + machine_mode mask_mode = get_mask_mode (GET_MODE (ops[1])); insn_expander e (op_num, /* HAS_DEST_P */ true, /* FULLY_UNMASKED_P */ true, @@ -1192,7 +1192,7 @@ static void emit_vlmax_fp_reduction_insn (unsigned icode, int op_num, rtx *ops) { machine_mode dest_mode = GET_MODE (ops[0]); - machine_mode mask_mode = get_mask_mode (GET_MODE (ops[1])).require (); + machine_mode mask_mode = get_mask_mode (GET_MODE (ops[1])); insn_expander e (op_num, /* HAS_DEST_P */ true, /* FULLY_UNMASKED_P */ true, @@ -1211,7 +1211,7 @@ static void emit_nonvlmax_fp_reduction_insn (unsigned icode, int op_num, rtx *ops, rtx vl) { machine_mode dest_mode = GET_MODE (ops[0]); - machine_mode mask_mode = get_mask_mode (GET_MODE (ops[1])).require (); + machine_mode mask_mode = get_mask_mode (GET_MODE (ops[1])); insn_expander e (op_num, /* HAS_DEST_P */ true, /* FULLY_UNMASKED_P */ false, @@ -1248,8 +1248,7 @@ void expand_vec_series (rtx dest, rtx base, rtx step) { machine_mode mode = GET_MODE (dest); - machine_mode mask_mode; - gcc_assert (get_mask_mode (mode).exists (&mask_mode)); + machine_mode mask_mode = get_mask_mode (mode); poly_int64 nunits_m1 = GET_MODE_NUNITS (mode) - 1; poly_int64 value; @@ -1789,10 +1788,10 @@ get_avl_type_rtx (enum avl_type type) /* Return the appropriate mask mode for MODE. */ -opt_machine_mode +machine_mode get_mask_mode (machine_mode mode) { - return get_vector_mode (BImode, GET_MODE_NUNITS (mode)); + return get_vector_mode (BImode, GET_MODE_NUNITS (mode)).require(); } /* Return the appropriate M1 mode for MODE. */ @@ -2318,8 +2317,7 @@ expand_vector_init_insert_elems (rtx target, const rvv_builder &builder, int nelts_reqd) { machine_mode mode = GET_MODE (target); - machine_mode mask_mode; - gcc_assert (get_mask_mode (mode).exists (&mask_mode)); + machine_mode mask_mode = get_mask_mode (mode); rtx dup = expand_vector_broadcast (mode, builder.elt (0)); emit_move_insn (target, dup); int ndups = builder.count_dups (0, nelts_reqd - 1, 1); @@ -2345,8 +2343,8 @@ expand_vector_init_merge_repeating_sequence (rtx target, const rvv_builder &builder) { machine_mode dup_mode = get_repeating_sequence_dup_machine_mode (builder); - machine_mode dup_mask_mode = get_mask_mode (dup_mode).require (); - machine_mode mask_mode = get_mask_mode (builder.mode ()).require (); + machine_mode dup_mask_mode = get_mask_mode (dup_mode); + machine_mode mask_mode = get_mask_mode (builder.mode ()); uint64_t full_nelts = builder.full_nelts ().to_constant (); /* Step 1: Broadcast the first pattern. */ @@ -2796,7 +2794,7 @@ expand_vec_perm (rtx target, rtx op0, rtx op1, rtx sel) __builtin_shufflevector (vec1, vec2, index...), the index can be any value in range of [0, 2 * nunits - 1]. */ machine_mode mask_mode; - mask_mode = get_mask_mode (data_mode).require (); + mask_mode = get_mask_mode (data_mode); rtx mask = gen_reg_rtx (mask_mode); max_sel = gen_const_vector_dup (sel_mode, nunits); @@ -2868,7 +2866,7 @@ shuffle_merge_patterns (struct expand_vec_perm_d *d) if (d->testing_p) return true; - machine_mode mask_mode = get_mask_mode (vmode).require (); + machine_mode mask_mode = get_mask_mode (vmode); rtx mask = gen_reg_rtx (mask_mode); rtx sel = vec_perm_indices_to_rtx (sel_mode, d->perm); @@ -2988,7 +2986,7 @@ shuffle_compress_patterns (struct expand_vec_perm_d *d) return false; /* Build a mask that is true when selector element is true. */ - machine_mode mask_mode = get_mask_mode (vmode).require (); + machine_mode mask_mode = get_mask_mode (vmode); rvv_builder builder (mask_mode, vlen, 1); for (int i = 0; i < vlen; i++) { @@ -3040,7 +3038,7 @@ static bool shuffle_decompress_patterns (struct expand_vec_perm_d *d) { poly_uint64 nelt = d->perm.length (); - machine_mode mask_mode = get_mask_mode (d->vmode).require (); + machine_mode mask_mode = get_mask_mode (d->vmode); /* For constant size indices, we dont't need to handle it here. Just leave it to vec_perm. */ @@ -3498,7 +3496,7 @@ expand_reduction (rtx_code code, rtx *ops, rtx init, reduction_type type) rtx vector = type == reduction_type::UNORDERED ? ops[1] : ops[2]; machine_mode vmode = GET_MODE (vector); machine_mode m1_mode = get_m1_mode (vmode).require (); - machine_mode m1_mmode = get_mask_mode (m1_mode).require (); + machine_mode m1_mmode = get_mask_mode (m1_mode); rtx m1_tmp = gen_reg_rtx (m1_mode); rtx m1_mask = gen_scalar_move_mask (m1_mmode); diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index dc78f4cf977..1eacca06b5c 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -7541,9 +7541,8 @@ riscv_support_vector_misalignment (machine_mode mode, static opt_machine_mode riscv_get_mask_mode (machine_mode mode) { - machine_mode mask_mode = VOIDmode; - if (TARGET_VECTOR && riscv_vector::get_mask_mode (mode).exists (&mask_mode)) - return mask_mode; + if (TARGET_VECTOR && riscv_v_ext_mode_p (mode)) + return riscv_vector::get_mask_mode (mode); return default_get_mask_mode (mode); } -- 2.40.1