From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mgamail.intel.com (unknown [134.134.136.20]) by sourceware.org (Postfix) with ESMTPS id 33BF93858CDA for ; Wed, 2 Aug 2023 07:59:43 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 33BF93858CDA Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1690963183; x=1722499183; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=YXvUCeQcfWbZBQKZ1CFZmMsEFMyO6W4WqHYfJDSwQQA=; b=irtyVF/mUjYCyuIiBbTSXRotDmWKMkbbFpnp9qacHu58oWiWug2dgFwt A2pU59HE59ZP4jo7MfB1BeRGpWY1hxPHWCZC8l06eCVF8YVxEmv4CgzQ6 KbpT9lUl1TkHyuJv2bW5bZH8DYCvlSIKj+WArXjuhoYMOn445WygTxlNL uMDSL2+sV/ooB5RRPWhCo8ksbf7W1fkokismaHYEMEI47wimGiEI+3fUE j3orbLy+twWp7Jfupe3kafNXzOSU8foPPTVBj8JW296c0ok82h3bSQGr7 3D+Hlw2ItwOp1Esyb0/tURDo/nZy3E6QkKQYJ/aBqWn0ekYfA4uZ8i3gQ A==; X-IronPort-AV: E=McAfee;i="6600,9927,10789"; a="359555283" X-IronPort-AV: E=Sophos;i="6.01,248,1684825200"; d="scan'208";a="359555283" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Aug 2023 00:59:28 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10789"; a="678974107" X-IronPort-AV: E=Sophos;i="6.01,248,1684825200"; d="scan'208";a="678974107" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by orsmga003.jf.intel.com with ESMTP; 02 Aug 2023 00:59:26 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id 753CF1007EA9; Wed, 2 Aug 2023 15:59:25 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@sifive.com, pan2.li@intel.com, yanzhang.wang@intel.com Subject: [PATCH v1] RISC-V: Enhance the test case for RVV vfsub/vfrsub rounding Date: Wed, 2 Aug 2023 15:59:24 +0800 Message-Id: <20230802075924.3448107-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Pan Li This patch would like to enhance the vfsub/vfrsub rounding API test for below 2 purposes. * The non-rm API has no frm related insn generated. * The rm API has the frm backup/restore/set insn generated. Signed-off-by: Pan Li gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-single-rsub.c: Enhance cases. * gcc.target/riscv/rvv/base/float-point-single-sub.c: Ditto. --- .../riscv/rvv/base/float-point-single-rsub.c | 16 +++++++++++++++- .../riscv/rvv/base/float-point-single-sub.c | 16 +++++++++++++++- 2 files changed, 30 insertions(+), 2 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-rsub.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-rsub.c index 1d770adc32c..86c56b7c6cb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-rsub.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-rsub.c @@ -16,4 +16,18 @@ test_vfrsub_vf_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, float32_t op2, return __riscv_vfrsub_vf_f32m1_rm_m (mask, op1, op2, 3, vl); } -/* { dg-final { scan-assembler-times {vfrsub\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 2 } } */ +vfloat32m1_t +test_vfrsub_vf_f32m1 (vfloat32m1_t op1, float32_t op2, size_t vl) { + return __riscv_vfrsub_vf_f32m1 (op1, op2, vl); +} + +vfloat32m1_t +test_vfrsub_vf_f32m1_m (vbool32_t mask, vfloat32m1_t op1, float32_t op2, + size_t vl) { + return __riscv_vfrsub_vf_f32m1_m (mask, op1, op2, vl); +} + +/* { dg-final { scan-assembler-times {vfrsub\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-sub.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-sub.c index 34ed03a31d9..8075dced0b9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-sub.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-sub.c @@ -27,4 +27,18 @@ test_vfsub_vf_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, float32_t op2, return __riscv_vfsub_vf_f32m1_rm_m (mask, op1, op2, 3, vl); } -/* { dg-final { scan-assembler-times {vfsub\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 4 } } */ +vfloat32m1_t +test_riscv_vfsub_vv_f32m1 (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) { + return __riscv_vfsub_vv_f32m1 (op1, op2, vl); +} + +vfloat32m1_t +test_vfsub_vv_f32m1_m (vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2, + size_t vl) { + return __riscv_vfsub_vv_f32m1_m (mask, op1, op2, vl); +} + +/* { dg-final { scan-assembler-times {vfsub\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 6 } } */ +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 4 } } */ -- 2.34.1