From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.136]) by sourceware.org (Postfix) with ESMTPS id 2FFD13858D1E for ; Sun, 6 Aug 2023 03:36:24 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 2FFD13858D1E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1691292984; x=1722828984; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=T1tMscml6UPvOikIOq2+1SYcLFa1YvHxTH6G8uye7tM=; b=Z3DFYy/+QT0jOSs8OWx/1r3X/GnbM7XX0YxmAlfsO1bMo0rq6vMfbXU9 2AoIFgJSFo9a2LgjLvN/Pvn5RRMVoLjWXJXqgzYycgXZO+JYm88/x3prf skL/sSgevgIIetrIvqp+7SmW2J1lGoRIBBfalg+k6r8l+/1HGAX47b8DT 3LghWzTQtJ1lTeE9BoS6iTkfAWcQo+Y8xomsI7DS04N3iC1Ut077vJpQg mVTJv/LUyDvcfe05UexHDITfER5CnDmPJvoYjzBcqChmZ5CDdUi7y4gs7 AGG1rnYWWRB0+ui0cvk6LPNOOPQayGE7LWLHOjGTIdh9Uvg7Cb44EYMUA A==; X-IronPort-AV: E=McAfee;i="6600,9927,10793"; a="349946553" X-IronPort-AV: E=Sophos;i="6.01,259,1684825200"; d="scan'208";a="349946553" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Aug 2023 20:36:22 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10793"; a="680407855" X-IronPort-AV: E=Sophos;i="6.01,259,1684825200"; d="scan'208";a="680407855" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by orsmga003.jf.intel.com with ESMTP; 05 Aug 2023 20:36:20 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id B6C5510054CB; Sun, 6 Aug 2023 11:36:19 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic Date: Sun, 6 Aug 2023 11:36:12 +0800 Message-Id: <20230806033612.1078855-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_ASCII_DIVIDERS,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Pan Li The frm_mode attr has some assumptions for each define insn as below. 1. The define insn has at least 9 operands. 2. The operands[9] must be frm reg. 3. The operands[9] must be const int. Actually, the frm operand can be operands[8], operands[9] or operands[10], and not all the define insn has frm operands. This patch would like to refactor frm and eliminate the above assumptions, as well as unblock the underlying rounding mode intrinsic API support. After refactor, the default frm will be none, and the selected insn type will be dyn. For the floating point which honors the frm, we will set the frm_mode attr explicitly in define_insn. Passed both the riscv.exp and rvv.exp for rv32/rv64 tests. Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv-protos.h (get_frm_mode): Remove operand assumptions. * config/riscv/riscv-v.cc (get_frm_mode): New function. * config/riscv/riscv-vector-builtins.cc (function_expander::use_ternop_insn): * config/riscv/vector.md: Set frm_mode attr explicitly. --- gcc/config/riscv/riscv-protos.h | 1 + gcc/config/riscv/riscv-v.cc | 28 ++++ gcc/config/riscv/riscv-vector-builtins.cc | 22 ++- gcc/config/riscv/vector.md | 170 ++++++++++++++-------- 4 files changed, 159 insertions(+), 62 deletions(-) diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 324991e2619..33f7cb1d670 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -236,6 +236,7 @@ bool check_builtin_call (location_t, vec, unsigned int, tree, unsigned int, tree *); bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT); bool legitimize_move (rtx, rtx); +int get_frm_mode (rtx); void emit_vlmax_vsetvl (machine_mode, rtx); void emit_hard_vlmax_vsetvl (machine_mode, rtx); void emit_vlmax_insn (unsigned, int, rtx *, rtx = 0); diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 278452b9e05..d5fb8611d6e 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -1513,6 +1513,34 @@ expand_const_vector (rtx target, rtx src) gcc_unreachable (); } +/* Get the frm mode with given CONST_INT rtx, the default mode is + FRM_MODE_DYN. */ +int +get_frm_mode (rtx operand) +{ + gcc_assert (CONST_INT_P (operand)); + + switch (INTVAL (operand)) + { + case FRM_RNE: + return FRM_MODE_RNE; + case FRM_RTZ: + return FRM_MODE_RTZ; + case FRM_RDN: + return FRM_MODE_RDN; + case FRM_RUP: + return FRM_MODE_RUP; + case FRM_RMM: + return FRM_MODE_RMM; + case FRM_DYN: + return FRM_MODE_DYN; + default: + return FRM_MODE_DYN; + } + + gcc_unreachable (); +} + /* Expand a pre-RA RVV data move from SRC to DEST. It expands move for RVV fractional vector modes. */ bool diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc index 528dca7ae85..abab06c00ed 100644 --- a/gcc/config/riscv/riscv-vector-builtins.cc +++ b/gcc/config/riscv/riscv-vector-builtins.cc @@ -3730,17 +3730,29 @@ function_expander::use_ternop_insn (bool vd_accum_p, insn_code icode) } for (int argno = arg_offset; argno < call_expr_nargs (exp); argno++) - add_input_operand (argno); + { + if (base->has_rounding_mode_operand_p () + && argno == call_expr_nargs (exp) - 2) + { + /* Since the rounding mode argument position is not consistent with + the instruction pattern, we need to skip rounding mode argument + here. */ + continue; + } + add_input_operand (argno); + } add_input_operand (Pmode, get_tail_policy_for_pred (pred)); add_input_operand (Pmode, get_mask_policy_for_pred (pred)); add_input_operand (Pmode, get_avl_type_rtx (avl_type::NONVLMAX)); - /* TODO: Currently, we don't support intrinsic that is modeling rounding mode. - We add default rounding mode for the intrinsics that didn't model rounding - mode yet. */ + if (base->has_rounding_mode_operand_p ()) + add_input_operand (call_expr_nargs (exp) - 2); + + /* The RVV floating-point only support dynamic rounding mode in the + FRM register. */ if (opno != insn_data[icode].n_generator_args) - add_input_operand (Pmode, const0_rtx); + add_input_operand (Pmode, gen_int_mode (riscv_vector::FRM_DYN, Pmode)); return generate_insn (icode); } diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 750b2de8df9..db3ee105ef4 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -867,26 +867,8 @@ (define_attr "vxrm_mode" "rnu,rne,rdn,rod,none" ;; Defines rounding mode of an floating-point operation. (define_attr "frm_mode" "rne,rtz,rdn,rup,rmm,dyn,dyn_exit,dyn_call,none" (cond [(eq_attr "type" "vfalu,vfwalu,vfmul,vfdiv,vfwmul") - (cond - [(match_test "INTVAL (operands[9]) == riscv_vector::FRM_RNE") - (const_string "rne") - - (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RTZ") - (const_string "rtz") - - (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RDN") - (const_string "rdn") - - (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RUP") - (const_string "rup") - - (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RMM") - (const_string "rmm") - - (match_test "INTVAL (operands[9]) == riscv_vector::FRM_DYN") - (const_string "dyn")] - (const_string "none"))] - (const_string "none"))) + (const_string "dyn")] + (const_string "none"))) ;; ----------------------------------------------------------------- ;; ---- Miscellaneous Operations @@ -6147,7 +6129,9 @@ (define_insn "@pred_" "TARGET_VECTOR" "vf.vv\t%0,%3,%4%p1" [(set_attr "type" "") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set (attr "frm_mode") + (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))]) (define_insn "@pred_" [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr") @@ -6190,7 +6174,9 @@ (define_insn "@pred__scalar" "TARGET_VECTOR" "vf.vf\t%0,%3,%4%p1" [(set_attr "type" "") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set (attr "frm_mode") + (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))]) (define_insn "@pred__scalar" [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr") @@ -6234,7 +6220,9 @@ (define_insn "@pred__scalar" "TARGET_VECTOR" "vf.vf\t%0,%3,%4%p1" [(set_attr "type" "") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set (attr "frm_mode") + (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))]) (define_insn "@pred__reverse_scalar" [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr") @@ -6257,7 +6245,9 @@ (define_insn "@pred__reverse_scalar" "TARGET_VECTOR" "vfr.vf\t%0,%3,%4%p1" [(set_attr "type" "") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set (attr "frm_mode") + (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))]) (define_insn "@pred_" [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr") @@ -6408,7 +6398,9 @@ (define_insn "*pred_" (set_attr "vl_op_idx" "5") (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])")) (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) - (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))]) + (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])")) + (set (attr "frm_mode") + (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))]) (define_insn "*pred_" [(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr") @@ -6441,7 +6433,9 @@ (define_insn "*pred_" (set_attr "vl_op_idx" "5") (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])")) (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) - (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))]) + (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])")) + (set (attr "frm_mode") + (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))]) (define_insn_and_rewrite "*pred_mul_" [(set (match_operand:VF 0 "register_operand" "=&vr, ?&vr") @@ -6478,7 +6472,9 @@ (define_insn_and_rewrite "*pred_mul_" operands[5] = operands[4] = operands[0]; } [(set_attr "type" "vfmuladd") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set (attr "frm_mode") + (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[10])"))]) (define_expand "@pred_mul__scalar" [(set (match_operand:VF 0 "register_operand") @@ -6535,7 +6531,9 @@ (define_insn "*pred__scalar" (set_attr "vl_op_idx" "5") (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])")) (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) - (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))]) + (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])")) + (set (attr "frm_mode") + (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))]) (define_insn "*pred__scalar" [(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr") @@ -6569,7 +6567,9 @@ (define_insn "*pred__scalar" (set_attr "vl_op_idx" "5") (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])")) (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) - (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))]) + (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])")) + (set (attr "frm_mode") + (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))]) (define_insn_and_rewrite "*pred_mul__scalar" [(set (match_operand:VF 0 "register_operand" "=&vr, ?&vr") @@ -6606,7 +6606,9 @@ (define_insn_and_rewrite "*pred_mul__scalar" operands[5] = operands[4] = operands[0]; } [(set_attr "type" "vfmuladd") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set (attr "frm_mode") + (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[10])"))]) (define_expand "@pred_mul_neg_" [(set (match_operand:VF 0 "register_operand") @@ -6668,7 +6670,9 @@ (define_insn "*pred_" (set_attr "vl_op_idx" "5") (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])")) (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) - (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))]) + (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])")) + (set (attr "frm_mode") + (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))]) (define_insn "*pred_" [(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr") @@ -6702,7 +6706,9 @@ (define_insn "*pred_" (set_attr "vl_op_idx" "5") (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])")) (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) - (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))]) + (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])")) + (set (attr "frm_mode") + (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))]) (define_insn_and_rewrite "*pred_mul_neg_" [(set (match_operand:VF 0 "register_operand" "=&vr, ?&vr") @@ -6740,7 +6746,9 @@ (define_insn_and_rewrite "*pred_mul_neg_" operands[5] = operands[4] = operands[0]; } [(set_attr "type" "vfmuladd") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set (attr "frm_mode") + (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[10])"))]) (define_expand "@pred_mul_neg__scalar" [(set (match_operand:VF 0 "register_operand") @@ -6799,7 +6807,9 @@ (define_insn "*pred__scalar" (set_attr "vl_op_idx" "5") (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])")) (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) - (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))]) + (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])")) + (set (attr "frm_mode") + (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))]) (define_insn "*pred__scalar" [(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr") @@ -6834,7 +6844,9 @@ (define_insn "*pred__scalar" (set_attr "vl_op_idx" "5") (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])")) (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) - (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))]) + (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])")) + (set (attr "frm_mode") + (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))]) (define_insn_and_rewrite "*pred_mul_neg__scalar" [(set (match_operand:VF 0 "register_operand" "=&vr, ?&vr") @@ -6872,7 +6884,9 @@ (define_insn_and_rewrite "*pred_mul_neg__scalar" operands[5] = operands[4] = operands[0]; } [(set_attr "type" "vfmuladd") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set (attr "frm_mode") + (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[10])"))]) ;; ------------------------------------------------------------------------------- ;; ---- Predicated floating-point unary operations @@ -6908,7 +6922,9 @@ (define_insn "@pred_" (set_attr "vl_op_idx" "4") (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])")) (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])")) - (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))]) + (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])")) + (set (attr "frm_mode") + (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))]) (define_insn "@pred_" [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr") @@ -7002,7 +7018,9 @@ (define_insn "@pred_dual_widen_" "TARGET_VECTOR" "vfw.vv\t%0,%3,%4%p1" [(set_attr "type" "vf") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set (attr "frm_mode") + (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))]) (define_insn "@pred_dual_widen__scalar" [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr") @@ -7027,7 +7045,9 @@ (define_insn "@pred_dual_widen__scalar" "TARGET_VECTOR" "vfw.vf\t%0,%3,%4%p1" [(set_attr "type" "vf") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set (attr "frm_mode") + (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))]) (define_insn "@pred_single_widen_add" [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr") @@ -7050,7 +7070,9 @@ (define_insn "@pred_single_widen_add" "TARGET_VECTOR" "vfwadd.wv\t%0,%3,%4%p1" [(set_attr "type" "vfwalu") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set (attr "frm_mode") + (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))]) (define_insn "@pred_single_widen_sub" [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr") @@ -7073,7 +7095,9 @@ (define_insn "@pred_single_widen_sub" "TARGET_VECTOR" "vfwsub.wv\t%0,%3,%4%p1" [(set_attr "type" "vfwalu") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set (attr "frm_mode") + (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))]) (define_insn "@pred_single_widen__scalar" [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr") @@ -7097,7 +7121,9 @@ (define_insn "@pred_single_widen__scalar" "TARGET_VECTOR" "vfw.wf\t%0,%3,%4%p1" [(set_attr "type" "vf") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set (attr "frm_mode") + (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))]) ;; ------------------------------------------------------------------------------- ;; ---- Predicated widen floating-point ternary operations @@ -7130,7 +7156,9 @@ (define_insn "@pred_widen_mul_" "TARGET_VECTOR" "vfw.vv\t%0,%3,%4%p1" [(set_attr "type" "vfwmuladd") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set (attr "frm_mode") + (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))]) (define_insn "@pred_widen_mul__scalar" [(set (match_operand:VWEXTF 0 "register_operand" "=&vr") @@ -7157,7 +7185,9 @@ (define_insn "@pred_widen_mul__scalar" "TARGET_VECTOR" "vfw.vf\t%0,%3,%4%p1" [(set_attr "type" "vfwmuladd") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set (attr "frm_mode") + (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))]) (define_insn "@pred_widen_mul_neg_" [(set (match_operand:VWEXTF 0 "register_operand" "=&vr") @@ -7184,7 +7214,9 @@ (define_insn "@pred_widen_mul_neg_" "TARGET_VECTOR" "vfw.vv\t%0,%3,%4%p1" [(set_attr "type" "vfwmuladd") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set (attr "frm_mode") + (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))]) (define_insn "@pred_widen_mul_neg__scalar" [(set (match_operand:VWEXTF 0 "register_operand" "=&vr") @@ -7212,7 +7244,9 @@ (define_insn "@pred_widen_mul_neg__scalar" "TARGET_VECTOR" "vfw.vf\t%0,%3,%4%p1" [(set_attr "type" "vfwmuladd") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set (attr "frm_mode") + (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))]) ;; ------------------------------------------------------------------------------- ;; ---- Predicated floating-point comparison operations @@ -7522,7 +7556,9 @@ (define_insn "@pred_fcvt_x_f" "TARGET_VECTOR" "vfcvt.x.f.v\t%0,%3%p1" [(set_attr "type" "vfcvtftoi") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set (attr "frm_mode") + (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))]) (define_insn "@pred_" [(set (match_operand: 0 "register_operand" "=vd, vd, vr, vr") @@ -7562,7 +7598,9 @@ (define_insn "@pred_" "TARGET_VECTOR" "vfcvt.f.x.v\t%0,%3%p1" [(set_attr "type" "vfcvtitof") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set (attr "frm_mode") + (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))]) ;; ------------------------------------------------------------------------------- ;; ---- Predicated floating-point widen conversions @@ -7590,7 +7628,9 @@ (define_insn "@pred_widen_fcvt_x_f" "TARGET_VECTOR" "vfwcvt.x.f.v\t%0,%3%p1" [(set_attr "type" "vfwcvtftoi") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set (attr "frm_mode") + (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))]) (define_insn "@pred_widen_" [(set (match_operand:VWCONVERTI 0 "register_operand" "=&vr, &vr") @@ -7675,7 +7715,9 @@ (define_insn "@pred_narrow_fcvt_x_f" "TARGET_VECTOR" "vfncvt.x.f.w\t%0,%3%p1" [(set_attr "type" "vfncvtftoi") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set (attr "frm_mode") + (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))]) (define_insn "@pred_narrow_" [(set (match_operand: 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr") @@ -7715,7 +7757,9 @@ (define_insn "@pred_narrow_" "TARGET_VECTOR" "vfncvt.f.x.w\t%0,%3%p1" [(set_attr "type" "vfncvtitof") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set (attr "frm_mode") + (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))]) (define_insn "@pred_trunc" [(set (match_operand: 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr") @@ -7736,7 +7780,9 @@ (define_insn "@pred_trunc" "TARGET_VECTOR" "vfncvt.f.f.w\t%0,%3%p1" [(set_attr "type" "vfncvtftof") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set (attr "frm_mode") + (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))]) (define_insn "@pred_rod_trunc" [(set (match_operand: 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr") @@ -8016,7 +8062,9 @@ (define_insn "@pred_reduc_plus" "TARGET_VECTOR" "vfredsum.vs\t%0,%3,%4%p1" [(set_attr "type" "vfred") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set (attr "frm_mode") + (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))]) ;; Float Ordered Reduction Sum for SF (define_insn "@pred_reduc_plus" @@ -8042,7 +8090,9 @@ (define_insn "@pred_reduc_plus" "TARGET_VECTOR" "vfredsum.vs\t%0,%3,%4%p1" [(set_attr "type" "vfred") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set (attr "frm_mode") + (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))]) ;; Float Ordered Reduction Sum for DF (define_insn "@pred_reduc_plus" @@ -8068,7 +8118,9 @@ (define_insn "@pred_reduc_plus" "TARGET_VECTOR" "vfredsum.vs\t%0,%3,%4%p1" [(set_attr "type" "vfred") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set (attr "frm_mode") + (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))]) ;; Float Widen Reduction for HF, aka SF = HF op SF (define_insn "@pred_widen_reduc_plus" @@ -8090,7 +8142,9 @@ (define_insn "@pred_widen_reduc_plus" "TARGET_VECTOR" "vfwredsum.vs\t%0,%3,%4%p1" [(set_attr "type" "vfwred") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set (attr "frm_mode") + (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))]) ;; Float Widen Reduction for SF, aka DF = SF * DF (define_insn "@pred_widen_reduc_plus" @@ -8112,7 +8166,9 @@ (define_insn "@pred_widen_reduc_plus" "TARGET_VECTOR" "vfwredsum.vs\t%0,%3,%4%p1" [(set_attr "type" "vfwred") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set (attr "frm_mode") + (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))]) ;; ------------------------------------------------------------------------------- ;; ---- Predicated permutation operations -- 2.34.1