From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.115]) by sourceware.org (Postfix) with ESMTPS id 70D983858280 for ; Mon, 7 Aug 2023 12:22:53 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 70D983858280 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1691410973; x=1722946973; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=3ueUfA91uWXzVUPL9HHMGQIh+ZHl0621D9JGOIoRvfA=; b=Jp2EIvtkIfOcOg89IAmC7dVaQMQchz6huVpVzHby0nAMMUDuLHQQSua7 N7qL/iiWTDjcOFrFTGXJhSphoojtr8X7GwZFUed5+BuUA51qOHmgFovX/ oem4yEbIIXPdqDggeObmzZeum4gSpmHrkIxQFVG6q8EXDXxsbJn2TwtwP 1+3YC8i2mXDKNWlDvS7drXKjkenGgkPsn+fWl9wW62lGHM+fHlL0ipeUm ozA8nMrc33OnhacC0apn5Oqz8QJb/usgtWtVNhgz8K57ZYzED4EKleD/2 K9KLAHFNeTi7dsqu7x1Fn7epss+UqqcnWTDRZmou7aldHnHJojlSAL8F+ Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10794"; a="370530625" X-IronPort-AV: E=Sophos;i="6.01,262,1684825200"; d="scan'208";a="370530625" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Aug 2023 05:22:52 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10794"; a="820980351" X-IronPort-AV: E=Sophos;i="6.01,262,1684825200"; d="scan'208";a="820980351" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by FMSMGA003.fm.intel.com with ESMTP; 07 Aug 2023 05:22:49 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 0A98010079B2; Mon, 7 Aug 2023 20:22:49 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@sifive.com, pan2.li@intel.com, yanzhang.wang@intel.com, jeffreyalaw@gmail.com Subject: [PATCH v1] Mode-Switching: Fix SET_SRC ICE when only one operand Date: Mon, 7 Aug 2023 20:22:47 +0800 Message-Id: <20230807122247.1881775-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Pan Li In same cases, like gcc/testsuite/gcc.dg/pr78148.c in RISC-V, there will be only 1 operand when SET_SRC in create_pre_exit. For example as below. (insn 13 9 14 2 (clobber (reg/i:TI 10 a0)) "gcc/testsuite/gcc.dg/pr78148.c":24:1 -1 (expr_list:REG_UNUSED (reg/i:TI 10 a0) (nil))) Unfortunately, SET_SRC requires at least 2 operands and then Segment Fault here. This patch would like to fix this ICE by adding operand length check before SET_SRC. Signed-off-by: Pan Li gcc/ChangeLog: * mode-switching.cc (create_pre_exit): Add operand length check. gcc/testsuite/ChangeLog: * gcc.target/riscv/mode-switch-ice-1.c: New test. --- gcc/mode-switching.cc | 2 ++ .../gcc.target/riscv/mode-switch-ice-1.c | 22 +++++++++++++++++++ 2 files changed, 24 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/mode-switch-ice-1.c diff --git a/gcc/mode-switching.cc b/gcc/mode-switching.cc index 64ae2bc29c3..cbf03c02159 100644 --- a/gcc/mode-switching.cc +++ b/gcc/mode-switching.cc @@ -411,6 +411,8 @@ create_pre_exit (int n_entities, int *entity_map, const int *num_modes) conflict with address reloads. */ if (copy_start >= ret_start && copy_start + copy_num <= ret_end + && GET_RTX_LENGTH (GET_CODE (return_copy_pat)) >= 2 + /* SET_SRC requires at least 2 operands. */ && OBJECT_P (SET_SRC (return_copy_pat))) forced_late_switch = true; break; diff --git a/gcc/testsuite/gcc.target/riscv/mode-switch-ice-1.c b/gcc/testsuite/gcc.target/riscv/mode-switch-ice-1.c new file mode 100644 index 00000000000..1b34a471904 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/mode-switch-ice-1.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +struct A { char e, f; }; + +struct B +{ + int g; + struct A h[4]; +}; + +extern void bar (int, int); + +struct B foo (void) +{ + bar (2, 1); +} + +void baz () +{ + foo (); +} -- 2.34.1