From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.20]) by sourceware.org (Postfix) with ESMTPS id 5201B3858D20 for ; Fri, 11 Aug 2023 07:19:12 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 5201B3858D20 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1691738352; x=1723274352; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=wbL+KPRDIMv+yifNXftaS3w56lIlqmgepfO7xWzA1Ss=; b=HBfKQOpzfVJrweaBcNOBmpc8DQCRlRvTUxg9+oqtIow3CqvkDBM9V2rH /C496y0NS5oOgI0pTR6lquc+gn+pKtLOUyTUCqil7h3Szi3boOd/LzCIy ql7qXG6g4wPDzcMXznp/ZKBxYgzIhbfRlIJN3qo5DOP3c13/ysSA37kS/ EaaaH/QXUOYovdh8PLIWKgEit63aUkvSvHTgcIvxxORCOtmsGiFeWL1mm AAzFZRawN80PQXv/gFAFjwOSra4f/DLopQdgrlHAcONM5A2Q/p2evqWhL kENk7HlxiAqWpf+Y171TuCZZfKeIXmFbFhmM5NFQjTeUHaGh9qkjBwmdf w==; X-IronPort-AV: E=McAfee;i="6600,9927,10798"; a="361753656" X-IronPort-AV: E=Sophos;i="6.01,164,1684825200"; d="scan'208";a="361753656" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Aug 2023 00:17:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10798"; a="767577580" X-IronPort-AV: E=Sophos;i="6.01,164,1684825200"; d="scan'208";a="767577580" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga001.jf.intel.com with ESMTP; 11 Aug 2023 00:17:50 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 8377B1007821; Fri, 11 Aug 2023 15:17:49 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, jeffreyalaw@gmail.com, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Support RVV VFMADD rounding mode intrinsic API Date: Fri, 11 Aug 2023 15:17:48 +0800 Message-Id: <20230811071748.486528-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Pan Li This patch would like to support the rounding mode API for the VFMADD as the below samples. * __riscv_vfmadd_vv_f32m1_rm * __riscv_vfmadd_vv_f32m1_rm_m * __riscv_vfmadd_vf_f32m1_rm * __riscv_vfmadd_vf_f32m1_rm_m Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (class vfmadd_frm): New class for vfmadd frm. (vfmadd_frm_obj): New declaration. (BASE): Ditto. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-functions.def (vfmadd_frm): New function definition. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-madd.c: New test. --- .../riscv/riscv-vector-builtins-bases.cc | 25 ++++++++++ .../riscv/riscv-vector-builtins-bases.h | 1 + .../riscv/riscv-vector-builtins-functions.def | 2 + .../riscv/rvv/base/float-point-madd.c | 47 +++++++++++++++++++ 4 files changed, 75 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-madd.c diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index 60c6e16f6ae..7476cdc317d 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -447,6 +447,29 @@ public: } }; +/* Implements below instructions for frm + - vfmadd +*/ +class vfmadd_frm : public function_base +{ +public: + bool has_rounding_mode_operand_p () const override { return true; } + + bool has_merge_operand_p () const override { return false; } + + rtx expand (function_expander &e) const override + { + if (e.op_info->op == OP_TYPE_vf) + return e.use_ternop_insn ( + false, code_for_pred_mul_scalar (PLUS, e.vector_mode ())); + if (e.op_info->op == OP_TYPE_vv) + return e.use_ternop_insn ( + false, code_for_pred_mul (PLUS, e.vector_mode ())); + + gcc_unreachable (); + } +}; + /* Implements vrsub. */ class vrsub : public function_base { @@ -2211,6 +2234,7 @@ static CONSTEXPR const vfmacc_frm vfmacc_frm_obj; static CONSTEXPR const vfnmsac vfnmsac_obj; static CONSTEXPR const vfnmsac_frm vfnmsac_frm_obj; static CONSTEXPR const vfmadd vfmadd_obj; +static CONSTEXPR const vfmadd_frm vfmadd_frm_obj; static CONSTEXPR const vfnmsub vfnmsub_obj; static CONSTEXPR const vfnmacc vfnmacc_obj; static CONSTEXPR const vfnmacc_frm vfnmacc_frm_obj; @@ -2450,6 +2474,7 @@ BASE (vfmacc_frm) BASE (vfnmsac) BASE (vfnmsac_frm) BASE (vfmadd) +BASE (vfmadd_frm) BASE (vfnmsub) BASE (vfnmacc) BASE (vfnmacc_frm) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h index 28eec2c3e99..5850ff0cf2e 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.h +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h @@ -164,6 +164,7 @@ extern const function_base *const vfmacc_frm; extern const function_base *const vfnmsac; extern const function_base *const vfnmsac_frm; extern const function_base *const vfmadd; +extern const function_base *const vfmadd_frm; extern const function_base *const vfnmsub; extern const function_base *const vfnmacc; extern const function_base *const vfnmacc_frm; diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def index c84e052c1a9..04f3de1275c 100644 --- a/gcc/config/riscv/riscv-vector-builtins-functions.def +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def @@ -357,6 +357,8 @@ DEF_RVV_FUNCTION (vfmsac_frm, alu_frm, full_preds, f_vvvv_ops) DEF_RVV_FUNCTION (vfmsac_frm, alu_frm, full_preds, f_vvfv_ops) DEF_RVV_FUNCTION (vfnmsac_frm, alu_frm, full_preds, f_vvvv_ops) DEF_RVV_FUNCTION (vfnmsac_frm, alu_frm, full_preds, f_vvfv_ops) +DEF_RVV_FUNCTION (vfmadd_frm, alu_frm, full_preds, f_vvvv_ops) +DEF_RVV_FUNCTION (vfmadd_frm, alu_frm, full_preds, f_vvfv_ops) // 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions DEF_RVV_FUNCTION (vfwmacc, alu, full_preds, f_wwvv_ops) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-madd.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-madd.c new file mode 100644 index 00000000000..00c9d002998 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-madd.c @@ -0,0 +1,47 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +typedef float float32_t; + +vfloat32m1_t +test_riscv_vfmadd_vv_f32m1_rm (vfloat32m1_t vd, vfloat32m1_t op1, + vfloat32m1_t op2, size_t vl) { + return __riscv_vfmadd_vv_f32m1_rm (vd, op1, op2, 0, vl); +} + +vfloat32m1_t +test_vfmadd_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t op1, + vfloat32m1_t op2, size_t vl) { + return __riscv_vfmadd_vv_f32m1_rm_m (mask, vd, op1, op2, 1, vl); +} + +vfloat32m1_t +test_vfmadd_vf_f32m1_rm (vfloat32m1_t vd, float32_t op1, vfloat32m1_t op2, + size_t vl) { + return __riscv_vfmadd_vf_f32m1_rm (vd, op1, op2, 2, vl); +} + +vfloat32m1_t +test_vfmadd_vf_f32m1_rm_m (vfloat32m1_t vd, vbool32_t mask, float32_t op1, + vfloat32m1_t op2, size_t vl) { + return __riscv_vfmadd_vf_f32m1_rm_m (mask, vd, op1, op2, 3, vl); +} + +vfloat32m1_t +test_riscv_vfmadd_vv_f32m1 (vfloat32m1_t vd, vfloat32m1_t op1, + vfloat32m1_t op2, size_t vl) { + return __riscv_vfmadd_vv_f32m1 (vd, op1, op2, vl); +} + +vfloat32m1_t +test_vfmadd_vv_f32m1_m (vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t op1, + vfloat32m1_t op2, size_t vl) { + return __riscv_vfmadd_vv_f32m1_m (mask, vd, op1, op2, vl); +} + +/* { dg-final { scan-assembler-times {vfmadd\.v[vf]\s+v[0-9]+,\s*[fav]+[0-9]+,\s*v[0-9]+} 6 } } */ +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 4 } } */ -- 2.34.1