From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pg1-x533.google.com (mail-pg1-x533.google.com [IPv6:2607:f8b0:4864:20::533]) by sourceware.org (Postfix) with ESMTPS id 302EC3858002 for ; Tue, 15 Aug 2023 18:29:20 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 302EC3858002 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pg1-x533.google.com with SMTP id 41be03b00d2f7-565f24a5c20so30721a12.1 for ; Tue, 15 Aug 2023 11:29:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1692124159; x=1692728959; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=Ol/xRDjpe/3vI7uquO8alW2UgIP6EESS1uEQ3tR4sbk=; b=HatCFMJaEkSRy4g941zTcj2KokFS9wNtY8w0ul2cC7ceia61wJONCfgzB5c0bnPEMF SAG6pMocdNXBRxtvSGW56z7LM/tHm5yVZpv/uM941U+AVm5BwALrm7BOp78c+eJ/0DAw zHgm9QCPFJXB3YDKLG47ZbdqWGS/weMmLu6oaPsESSI+EIZJ3GR/ktXcb7TTxbtsmBVb lBsYoBMxhReKt1IGbdwx8FJcHhOKUw3KsCAln1pbb2/gt/a/J4cacxwNQUDV5ZeGWFy5 rLeYDtXRCT//pxkUDKkO76kFpKP5Sk6xG/uTt9HIVOJlorhttIRUMwRuCg1d0VDLcMPY BezA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692124159; x=1692728959; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=Ol/xRDjpe/3vI7uquO8alW2UgIP6EESS1uEQ3tR4sbk=; b=N162fYmx+ZSoXhZ6V3LKNCl7ffIpKg0s/gZZil9H6nFBn68fl2xatpZVYfLQQmDYX4 VlcYCb7LialuR55NGq1rSg4PE9rTUZ/9aC/ajH8ZC42ERQuZb4Y0CV2or1jllCNQ1S+D 4C1HQ+DkumYcJbpYyGd9IhubYw6HSsOx+v9H1kxgWzB+wg0DGB93i4G9IuwYDWe1UP3m 7IDWcePOlbp6yXIRBFgdp6rAN58jeETvUlOX+agb2updZWsvrnZDMmuWbTrYLzJj8uAv eiWKod5xap0/GJjjckZK34Hz2yBBG2E8W/e4/ozkRIdGWl83noQH6KLRm+KxuKkrlEAL 7Zww== X-Gm-Message-State: AOJu0YwIhnbnEy9sUmPUtlqN6joq2yJCAhgxDNOBkH6Qv6Ct+ldSfljl nBFyFdoCPflzTCbLmm5caUXHEzvow0pClg40amGTGw== X-Google-Smtp-Source: AGHT+IHysaVS97IlQltQWuc1DZEB5fnE2MhJLyfz/ei99UsFabX/geLVvqGKhzDlpiavQSkkA0SrVg== X-Received: by 2002:a05:6a20:7d97:b0:13f:c159:63ec with SMTP id v23-20020a056a207d9700b0013fc15963ecmr3484103pzj.24.1692124158348; Tue, 15 Aug 2023 11:29:18 -0700 (PDT) Received: from ewlu.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id c10-20020a63724a000000b0056416526a5csm10300721pgn.59.2023.08.15.11.29.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Aug 2023 11:29:17 -0700 (PDT) From: Edwin Lu To: gcc-patches@gcc.gnu.org Cc: gnu-toolchain@rivosinc.com, Edwin Lu , Vineet Gupta Subject: [PATCH V3] riscv: generate builtin macro for compilation with strict alignment: Date: Tue, 15 Aug 2023 11:29:10 -0700 Message-ID: <20230815182913.2824479-1-ewlu@rivosinc.com> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This patch is a modification of https://gcc.gnu.org/pipermail/gcc-patches/2023-January/610115.html following the discussion on https://github.com/riscv-non-isa/riscv-c-api-doc/issues/32 Distinguish between explicit -mstrict-align and cpu tune param for slow_unaligned_access=true/false. Tested for regressions using rv32/64 multilib with newlib/linux gcc/ChangeLog: * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Generate __riscv_unaligned_avoid with value 1 or __riscv_unaligned_slow with value 1 or __riscv_unaligned_fast with value 1 * config/riscv/riscv.cc (riscv_option_override): Define riscv_user_wants_strict_align. Set riscv_user_wants_strict_align to TARGET_STRICT_ALIGN * config/riscv/riscv.h: Declare riscv_user_wants_strict_align gcc/testsuite/ChangeLog: * gcc.target/riscv/attribute-1.c: Check for __riscv_unaligned_slow or __riscv_unaligned_fast * gcc.target/riscv/attribute-4.c: Check for __riscv_unaligned_avoid * gcc.target/riscv/attribute-5.c: Check for __riscv_unaligned_slow or __riscv_unaligned_fast * gcc.target/riscv/predef-align-1.c: New test. * gcc.target/riscv/predef-align-2.c: New test. * gcc.target/riscv/predef-align-3.c: New test. * gcc.target/riscv/predef-align-4.c: New test. * gcc.target/riscv/predef-align-5.c: New test. * gcc.target/riscv/predef-align-6.c: New test. Signed-off-by: Edwin Lu Co-authored-by: Vineet Gupta --- Changes in V3: - Clean up tests to be less verbose - Fix style, comments, and consistency Changes in V2: - Updated naming conventions - Updated tests when -m[no-]strict-align is not explicitly added --- gcc/config/riscv/riscv-c.cc | 7 +++++++ gcc/config/riscv/riscv.cc | 9 +++++++++ gcc/config/riscv/riscv.h | 1 + gcc/testsuite/gcc.target/riscv/attribute-1.c | 12 ++++++++++++ gcc/testsuite/gcc.target/riscv/attribute-4.c | 10 ++++++++++ gcc/testsuite/gcc.target/riscv/attribute-5.c | 11 +++++++++++ gcc/testsuite/gcc.target/riscv/predef-align-1.c | 16 ++++++++++++++++ gcc/testsuite/gcc.target/riscv/predef-align-2.c | 15 +++++++++++++++ gcc/testsuite/gcc.target/riscv/predef-align-3.c | 16 ++++++++++++++++ gcc/testsuite/gcc.target/riscv/predef-align-4.c | 16 ++++++++++++++++ gcc/testsuite/gcc.target/riscv/predef-align-5.c | 15 +++++++++++++++ gcc/testsuite/gcc.target/riscv/predef-align-6.c | 16 ++++++++++++++++ 12 files changed, 144 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/predef-align-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/predef-align-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/predef-align-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/predef-align-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/predef-align-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/predef-align-6.c diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc index 2937c160071..283052ae313 100644 --- a/gcc/config/riscv/riscv-c.cc +++ b/gcc/config/riscv/riscv-c.cc @@ -108,6 +108,13 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile) } + if (riscv_user_wants_strict_align) + builtin_define_with_int_value ("__riscv_unaligned_avoid", 1); + else if (riscv_slow_unaligned_access_p) + builtin_define_with_int_value ("__riscv_unaligned_slow", 1); + else + builtin_define_with_int_value ("__riscv_unaligned_fast", 1); + if (TARGET_MIN_VLEN != 0) builtin_define_with_int_value ("__riscv_v_min_vlen", TARGET_MIN_VLEN); diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 49062bef9fc..705b750aaad 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -247,6 +247,9 @@ struct riscv_tune_info { /* Whether unaligned accesses execute very slowly. */ bool riscv_slow_unaligned_access_p; +/* Whether user explicitly passed -mstrict-align. */ +bool riscv_user_wants_strict_align; + /* Stack alignment to assume/maintain. */ unsigned riscv_stack_boundary; @@ -6962,6 +6965,12 @@ riscv_option_override (void) -m[no-]strict-align is left unspecified, heed -mtune's advice. */ riscv_slow_unaligned_access_p = (cpu->tune_param->slow_unaligned_access || TARGET_STRICT_ALIGN); + + /* Make a note if user explicity passed -mstrict-align for later + builtin macro generation. Can't use target_flags_explicitly since + it is set even for -mno-strict-align. */ + riscv_user_wants_strict_align = TARGET_STRICT_ALIGN; + if ((target_flags_explicit & MASK_STRICT_ALIGN) == 0 && cpu->tune_param->slow_unaligned_access) target_flags |= MASK_STRICT_ALIGN; diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index e18a0081297..e093db09d31 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -1036,6 +1036,7 @@ while (0) #ifndef USED_FOR_TARGET extern const enum reg_class riscv_regno_to_class[]; extern bool riscv_slow_unaligned_access_p; +extern bool riscv_user_wants_strict_align; extern unsigned riscv_stack_boundary; extern unsigned riscv_bytes_per_vector_chunk; extern poly_uint16 riscv_vector_chunks; diff --git a/gcc/testsuite/gcc.target/riscv/attribute-1.c b/gcc/testsuite/gcc.target/riscv/attribute-1.c index bc919c586b6..abfb0b498e0 100644 --- a/gcc/testsuite/gcc.target/riscv/attribute-1.c +++ b/gcc/testsuite/gcc.target/riscv/attribute-1.c @@ -2,5 +2,17 @@ /* { dg-options "-mriscv-attribute" } */ int foo() { + +/* In absence of -m[no-]strict-align, default mcpu is currently + set to rocket. rocket has slow_unaligned_access=true. */ +#if !defined(__riscv_unaligned_slow) +#error "__riscv_unaligned_slow is not set" +#endif + +#if defined(__riscv_unaligned_avoid) || defined(__riscv_unaligned_fast) +#error "__riscv_unaligned_avoid or __riscv_unaligned_fast is unexpectedly set" +#endif + +return 0; } /* { dg-final { scan-assembler ".attribute arch" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-4.c b/gcc/testsuite/gcc.target/riscv/attribute-4.c index 7c565c4963e..545f87cb899 100644 --- a/gcc/testsuite/gcc.target/riscv/attribute-4.c +++ b/gcc/testsuite/gcc.target/riscv/attribute-4.c @@ -2,5 +2,15 @@ /* { dg-options "-mriscv-attribute -mstrict-align" } */ int foo() { + +#if !defined(__riscv_unaligned_avoid) +#error "__riscv_unaligned_avoid is not set" +#endif + +#if defined(__riscv_unaligned_fast) || defined(__riscv_unaligned_slow) +#error "__riscv_unaligned_fast or __riscv_unaligned_slow is unexpectedly set" +#endif + + return 0; } /* { dg-final { scan-assembler ".attribute unaligned_access, 0" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-5.c b/gcc/testsuite/gcc.target/riscv/attribute-5.c index ee9cf693be6..753043c31e9 100644 --- a/gcc/testsuite/gcc.target/riscv/attribute-5.c +++ b/gcc/testsuite/gcc.target/riscv/attribute-5.c @@ -2,5 +2,16 @@ /* { dg-options "-mriscv-attribute -mno-strict-align" } */ int foo() { + +/* Default mcpu is rocket which has slow_unaligned_access=true. */ +#if !defined(__riscv_unaligned_slow) +#error "__riscv_unaligned_slow is not set" +#endif + +#if defined(__riscv_unaligned_avoid) || defined(__riscv_unaligned_fast) +#error "__riscv_unaligned_avoid or __riscv_unaligned_fast is unexpectedly set" +#endif + +return 0; } /* { dg-final { scan-assembler ".attribute unaligned_access, 1" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/predef-align-1.c b/gcc/testsuite/gcc.target/riscv/predef-align-1.c new file mode 100644 index 00000000000..9dde37a721e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/predef-align-1.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-mtune=thead-c906" } */ + +int main() { + +/* thead-c906 default is cpu tune param unaligned access fast */ +#if !defined(__riscv_unaligned_fast) +#error "__riscv_unaligned_fast is not set" +#endif + +#if defined(__riscv_unaligned_avoid) || defined(__riscv_unaligned_slow) +#error "__riscv_unaligned_avoid or __riscv_unaligned_slow is unexpectedly set" +#endif + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/predef-align-2.c b/gcc/testsuite/gcc.target/riscv/predef-align-2.c new file mode 100644 index 00000000000..33d604f5aa0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/predef-align-2.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mtune=thead-c906 -mstrict-align" } */ + +int main() { + +#if !defined(__riscv_unaligned_avoid) +#error "__riscv_unaligned_avoid is not set" +#endif + +#if defined(__riscv_unaligned_fast) || defined(__riscv_unaligned_slow) +#error "__riscv_unaligned_fast or __riscv_unaligned_slow is unexpectedly set" +#endif + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/predef-align-3.c b/gcc/testsuite/gcc.target/riscv/predef-align-3.c new file mode 100644 index 00000000000..daf5718a39f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/predef-align-3.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-mtune=thead-c906 -mno-strict-align" } */ + +int main() { + +/* thead-c906 default is cpu tune param unaligned access fast */ +#if !defined(__riscv_unaligned_fast) +#error "__riscv_unaligned_fast is not set" +#endif + +#if defined(__riscv_unaligned_avoid) || defined(__riscv_unaligned_slow) +#error "__riscv_unaligned_avoid or __riscv_unaligned_slow is unexpectedly set" +#endif + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/predef-align-4.c b/gcc/testsuite/gcc.target/riscv/predef-align-4.c new file mode 100644 index 00000000000..d46a46f252d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/predef-align-4.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-mtune=rocket" } */ + +int main() { + +/* rocket default is cpu tune param unaligned access slow */ +#if !defined(__riscv_unaligned_slow) +#error "__riscv_unaligned_slow is not set" +#endif + +#if defined(__riscv_unaligned_avoid) || defined(__riscv_unaligned_fast) +#error "__riscv_unaligned_avoid or __riscv_unaligned_fast is unexpectedly set" +#endif + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/predef-align-5.c b/gcc/testsuite/gcc.target/riscv/predef-align-5.c new file mode 100644 index 00000000000..3aa25f8e0e0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/predef-align-5.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mtune=rocket -mstrict-align" } */ + +int main() { + +#if !defined(__riscv_unaligned_avoid) +#error "__riscv_unaligned_avoid is not set" +#endif + +#if defined(__riscv_unaligned_fast) || defined(__riscv_unaligned_slow) +#error "__riscv_unaligned_fast or __riscv_unaligned_slow is unexpectedly set" +#endif + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/predef-align-6.c b/gcc/testsuite/gcc.target/riscv/predef-align-6.c new file mode 100644 index 00000000000..cb64d7e7778 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/predef-align-6.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-mtune=rocket -mno-strict-align" } */ + +int main() { + +/* rocket default is cpu tune param unaligned access slow */ +#if !defined(__riscv_unaligned_slow) +#error "__riscv_unaligned_slow is not set" +#endif + +#if defined(__riscv_unaligned_avoid) || defined(__riscv_unaligned_fast) +#error "__riscv_unaligned_avoid or __riscv_unaligned_fast is unexpectedly set" +#endif + + return 0; +} -- 2.34.1