From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.93]) by sourceware.org (Postfix) with ESMTPS id 022C63858C52 for ; Wed, 16 Aug 2023 08:10:13 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 022C63858C52 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1692173414; x=1723709414; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Gyp5ttDM8qQ3aJqs0a3gaBxLB4eFT12JgEcoTliJ8iw=; b=aSPQjIX9u1lyh0K9jrCWs9ktO0kMPIIiQ3OpoV9ucbOEvXaoQ8c+p83a Dkt5nDu60zGjSxv/przECbggRXIkFjRJrPvDaPnntnlY3LTvC1wpNMVpC j8IFy0AY6goOsx+D9+H09EnMpEtT5WoUXh6F1iEvWDCTMxR3hLRr9fzG8 7jxyhh+cAxZg+4LOGX3I04xsjiCGjTK5YdJLMxZmWn4ZgVfRkJki38ZAY 2KaIcTBLs7o0+xipYYtlzHRdvNwE1H/AyyKBV0z1QTYFyv4r0wVrx6+iy Ev/ucf16FavvlM9APKFrTsUlQIeFf77frCpm0oigRm73KgbIIjlS4uoVD A==; X-IronPort-AV: E=McAfee;i="6600,9927,10803"; a="369945112" X-IronPort-AV: E=Sophos;i="6.01,176,1684825200"; d="scan'208";a="369945112" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Aug 2023 01:10:12 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10803"; a="857721410" X-IronPort-AV: E=Sophos;i="6.01,176,1684825200"; d="scan'208";a="857721410" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga004.jf.intel.com with ESMTP; 16 Aug 2023 01:10:09 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 1035F1005138; Wed, 16 Aug 2023 16:10:09 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@sifive.com, pan2.li@intel.com, yanzhang.wang@intel.com Subject: [PATCH v2] RISC-V: Support RVV VFWCVT.XU.F.V rounding mode intrinsic API Date: Wed, 16 Aug 2023 16:10:07 +0800 Message-Id: <20230816081007.1211587-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230815090730.2537591-1-pan2.li@intel.com> References: <20230815090730.2537591-1-pan2.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Pan Li This patch would like to support the rounding mode API for the VFWCVT.X.F.V as the below samples. * __riscv_vfwcvt_xu_f_v_u64m2_rm * __riscv_vfwcvt_xu_f_v_u64m2_rm_m Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (BASE): New declaration. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-functions.def (vfwcvt_xu_frm): New intrinsic function def. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-wcvt-xu.c: New test. --- .../riscv/riscv-vector-builtins-bases.cc | 2 ++ .../riscv/riscv-vector-builtins-bases.h | 1 + .../riscv/riscv-vector-builtins-functions.def | 1 + .../riscv/rvv/base/float-point-wcvt-xu.c | 29 +++++++++++++++++++ 4 files changed, 33 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wcvt-xu.c diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index 22640745398..6621c77c3f2 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -2497,6 +2497,7 @@ static CONSTEXPR const vfcvt_f vfcvt_f_frm_obj; static CONSTEXPR const vfwcvt_x vfwcvt_x_obj; static CONSTEXPR const vfwcvt_x vfwcvt_x_frm_obj; static CONSTEXPR const vfwcvt_x vfwcvt_xu_obj; +static CONSTEXPR const vfwcvt_x vfwcvt_xu_frm_obj; static CONSTEXPR const vfwcvt_rtz_x vfwcvt_rtz_x_obj; static CONSTEXPR const vfwcvt_rtz_x vfwcvt_rtz_xu_obj; static CONSTEXPR const vfwcvt_f vfwcvt_f_obj; @@ -2750,6 +2751,7 @@ BASE (vfcvt_f_frm) BASE (vfwcvt_x) BASE (vfwcvt_x_frm) BASE (vfwcvt_xu) +BASE (vfwcvt_xu_frm) BASE (vfwcvt_rtz_x) BASE (vfwcvt_rtz_xu) BASE (vfwcvt_f) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h index dd711846cbe..6565740c597 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.h +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h @@ -215,6 +215,7 @@ extern const function_base *const vfcvt_f_frm; extern const function_base *const vfwcvt_x; extern const function_base *const vfwcvt_x_frm; extern const function_base *const vfwcvt_xu; +extern const function_base *const vfwcvt_xu_frm; extern const function_base *const vfwcvt_rtz_x; extern const function_base *const vfwcvt_rtz_xu; extern const function_base *const vfwcvt_f; diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def index 4e6cc793447..22c039c8cbb 100644 --- a/gcc/config/riscv/riscv-vector-builtins-functions.def +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def @@ -460,6 +460,7 @@ DEF_RVV_FUNCTION (vfwcvt_f, alu, full_preds, u_to_wf_xu_v_ops) DEF_RVV_FUNCTION (vfwcvt_f, alu, full_preds, f_to_wf_f_v_ops) DEF_RVV_FUNCTION (vfwcvt_x_frm, alu_frm, full_preds, f_to_wi_f_v_ops) +DEF_RVV_FUNCTION (vfwcvt_xu_frm, alu_frm, full_preds, f_to_wu_f_v_ops) // 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions DEF_RVV_FUNCTION (vfncvt_x, narrow_alu, full_preds, f_to_ni_f_w_ops) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wcvt-xu.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wcvt-xu.c new file mode 100644 index 00000000000..29449e79b69 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wcvt-xu.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +vuint64m2_t +test_riscv_vfwcvt_xu_f_v_u64m2_rm (vfloat32m1_t op1, size_t vl) { + return __riscv_vfwcvt_xu_f_v_u64m2_rm (op1, 0, vl); +} + +vuint64m2_t +test_vfwcvt_xu_f_v_u64m2_rm_m (vbool32_t mask, vfloat32m1_t op1, size_t vl) { + return __riscv_vfwcvt_xu_f_v_u64m2_rm_m (mask, op1, 1, vl); +} + +vuint64m2_t +test_riscv_vfwcvt_xu_f_v_u64m2 (vfloat32m1_t op1, size_t vl) { + return __riscv_vfwcvt_xu_f_v_u64m2 (op1, vl); +} + +vuint64m2_t +test_vfwcvt_xu_f_v_u64m2_m (vbool32_t mask, vfloat32m1_t op1, size_t vl) { + return __riscv_vfwcvt_xu_f_v_u64m2_m (mask, op1, vl); +} + +/* { dg-final { scan-assembler-times {vfwcvt\.xu\.f\.v\s+v[0-9]+,\s*v[0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */ -- 2.34.1