From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf1-x443.google.com (mail-pf1-x443.google.com [IPv6:2607:f8b0:4864:20::443]) by sourceware.org (Postfix) with ESMTPS id 450D43858C2C for ; Thu, 17 Aug 2023 01:17:39 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 450D43858C2C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pf1-x443.google.com with SMTP id d2e1a72fcca58-68879fc4871so1369957b3a.0 for ; Wed, 16 Aug 2023 18:17:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1692235057; x=1692839857; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4DZ3F+/Rq2/glNphffGh5KApuzqLKjRapBOcilHRNzU=; b=bjf7S8jOhwbWIMfAfwXCPolXC+slPNABl2lxIaGsC3e3dOfvEjsLPr5n+0dJECrFOz EEA1/Mfv+MiMfL0W+hwcyqyre5YD6aWMaDiDHr/OXRdqNDgZGZbiP/Nrc0GTkE/wk0XF zja1DOrYofG9b0PFn/prC/6HiueSnUYhEem8w6RrY82e6sCQybG4FPLKLmyX9YH4+bqS /dZ8OQhuAbtTEnd2Lk4twGmcrqGqcnx3gczKzRvOV9+xGoWKOZCIhSocYL9AuvPsna6D iUP8ZtjuNfRcNXVZqd8GbbemlLKa7YvDXb8NY5iGYejJO8NhXYhGlx8G4ehLQNBf7v5+ gt6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692235057; x=1692839857; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4DZ3F+/Rq2/glNphffGh5KApuzqLKjRapBOcilHRNzU=; b=UEQAdHvIczUJ5c0uQLMksSH2sxfx3WphueyBOWcaDvLQzfBkOvLN9JfBEd/0Otsu9e Zmym3NIGQa19yeGxtyUqidz3+1TgYY08MFsS3WHarO2BLHAIwpiRYpovWix5/be0YWyR 0BktQTlfeaQs20e8Daj+2rvQZiNx0uc9Cq5jGl/sjBQoPVrWlXos19PSs19+fUTmZjD6 v0+XaOnL426YLBIUp4E8Jn/4JlizMOy5MvYzWYTxtClde8jA8sVXfKXdRgqzkAyGFyYB D7gzbvN1uyzK/OeCFooXXWRaAum2JW0nlSU8i0T698AEMhGLA9WHgGBTB9uzyxlFRKjk eRhQ== X-Gm-Message-State: AOJu0Ywt8Mh7ardjY1LjfgOY+rC2xpA66eNWLILJtC0eSy63ZFa9Laa2 qV+2Dj6q8IWZB8uO/uFoN4mbMUelwN9Fa9Yup2wOhHJL X-Google-Smtp-Source: AGHT+IESgZD9ievzxyKObD/M3V7gLRGIQmFjWQDCF3Fnw8GJQgUXEeDFfKHw8BoPJMD28h/JAN1BDA== X-Received: by 2002:a05:6a20:3c91:b0:134:a478:5e4a with SMTP id b17-20020a056a203c9100b00134a4785e4amr4377399pzj.17.1692235057005; Wed, 16 Aug 2023 18:17:37 -0700 (PDT) Received: from patrick-ThinkPad-X1-Carbon-Gen-8.hq.rivosinc.com ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id u18-20020aa78492000000b00689e910ddd9sm139594pfn.57.2023.08.16.18.17.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Aug 2023 18:17:36 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org, pinskia@gmail.com Cc: wangfeng@eswincomputing.com, jeffreyalaw@gmail.com, gnu-toolchain@rivosinc.com, palmer@rivosinc.com, charlie@rivosinc.com, Patrick O'Neill Subject: [PATCH v2] RISCV: Add rotate immediate regression test Date: Wed, 16 Aug 2023 18:17:29 -0700 Message-Id: <20230817011729.324315-1-patrick@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230816231403.321156-1-patrick@rivosinc.com> References: <20230816231403.321156-1-patrick@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This adds new regression tests to ensure half-register rotations are correctly optimized into rori instructions. gcc/testsuite/ChangeLog: * gcc.target/riscv/zbb-rol-ror-08.c: New test. * gcc.target/riscv/zbb-rol-ror-09.c: New test. Co-authored-by: Charlie Jenkins Signed-off-by: Patrick O'Neill --- Trunk optimized these added testcases correctly. GCC 13.2 and earlier do not optimize these cases correctly. Expands on testcases added in: https://gcc.gnu.org/git/?p=gcc.git;a=commit;f=gcc/testsuite/gcc.target/riscv/zbb-rol-ror-04.c;h=0ccf520d349a82dafca0deb3d307a1080e8589a0 --- V2 Changes: Move testcases to new files. --- .../gcc.target/riscv/zbb-rol-ror-08.c | 25 +++++++++++++++++++ .../gcc.target/riscv/zbb-rol-ror-09.c | 15 +++++++++++ 2 files changed, 40 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-rol-ror-08.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-rol-ror-09.c diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-08.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-08.c new file mode 100644 index 00000000000..30696f3bb32 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-08.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zbb -mabi=lp64d -fno-lto -O2" } */ +/* { dg-skip-if "" { *-*-* } { "-g" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-final { scan-assembler-not "and" } } */ + +/* +**foo1: +** rori a0,a0,32 +** ret +*/ +unsigned long foo1(unsigned long rotate) +{ + return (rotate << 32) | (rotate >> 32); +} + +/* +**foo2: +** roriw a0,a0,16 +** ret +*/ +unsigned int foo2(unsigned int rotate) +{ + return (rotate << 16) | (rotate >> 16); +} diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-09.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-09.c new file mode 100644 index 00000000000..a3054553e18 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-09.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zbb -mabi=ilp32 -fno-lto -O2" } */ +/* { dg-skip-if "" { *-*-* } { "-g" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-final { scan-assembler-not "and" } } */ + +/* +**foo1: +** rori a0,a0,16 +** ret +*/ +unsigned int foo1(unsigned int rs1) +{ + return (rs1 << 16) | (rs1 >> 16); +} -- 2.34.1