* [PATCH] RISC-V: Add attribute to vtype change only vsetvl
@ 2023-08-23 2:11 Juzhe-Zhong
0 siblings, 0 replies; only message in thread
From: Juzhe-Zhong @ 2023-08-23 2:11 UTC (permalink / raw)
To: gcc-patches; +Cc: kito.cheng, kito.cheng, Juzhe-Zhong
This patch is prepare patch for VSETVL PASS.
Commited.
gcc/ChangeLog:
* config/riscv/vector.md: Add attribute.
---
gcc/config/riscv/vector.md | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index e772e79057d..6ceae25dbed 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -1363,7 +1363,11 @@
"TARGET_VECTOR"
"vsetvli\tzero,zero,e%0,%m1,t%p2,m%p3"
[(set_attr "type" "vsetvl")
- (set_attr "mode" "SI")])
+ (set_attr "mode" "SI")
+ (set (attr "sew") (symbol_ref "INTVAL (operands[0])"))
+ (set (attr "vlmul") (symbol_ref "INTVAL (operands[1])"))
+ (set (attr "ta") (symbol_ref "INTVAL (operands[2])"))
+ (set (attr "ma") (symbol_ref "INTVAL (operands[3])"))])
;; vsetvl zero,rs1,vtype instruction.
;; The reason we need this pattern since we should avoid setting X0 register
--
2.36.3
^ permalink raw reply [flat|nested] only message in thread
only message in thread, other threads:[~2023-08-23 2:11 UTC | newest]
Thread overview: (only message) (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-08-23 2:11 [PATCH] RISC-V: Add attribute to vtype change only vsetvl Juzhe-Zhong
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).