From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.20]) by sourceware.org (Postfix) with ESMTPS id 950CB3858C53 for ; Thu, 24 Aug 2023 04:49:16 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 950CB3858C53 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1692852556; x=1724388556; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=ynQlpCasgdJ/f0gp7n2qo+pF6Iewt/HFBfbT0FBe0zk=; b=d8aywIpCrDimRvmIpt4bJZtu/G6KjtPgScTUE+g2cjQ93YYm5UOLKlEA O2dFBhMeUQAMyFWb2AkYOHewwKjL2Ircb+jsUP8jZ1+oM63pVaZ7Wxaf3 ZmUoGsebzYyvz1HwKwdUceH+VORprgczU58Xk2EfyXIZx8VXMN6Y33cbV FQYloSb5N3ArEgODdGElhhe6dHExf13iYixW905ybKf49d+eWrRJRDXMs kUyFqtYRFdq20e7e5KC6Q7b1axd6zPQCWFz47zfBTjpvyF++YbaIzvBwx A6fHPp8QUvpO+d04h4jQ3FtF1CoclJXRQuXwG7hdgyUqgF3PkHSzfAVtP g==; X-IronPort-AV: E=McAfee;i="6600,9927,10811"; a="364515263" X-IronPort-AV: E=Sophos;i="6.01,195,1684825200"; d="scan'208";a="364515263" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Aug 2023 21:49:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10811"; a="740029180" X-IronPort-AV: E=Sophos;i="6.01,195,1684825200"; d="scan'208";a="740029180" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga007.fm.intel.com with ESMTP; 23 Aug 2023 21:49:13 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 38CB71007810; Thu, 24 Aug 2023 12:49:12 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Support rounding mode for VFMADD/VFMACC autovec Date: Thu, 24 Aug 2023 12:49:07 +0800 Message-Id: <20230824044907.4078472-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_ASCII_DIVIDERS,KAM_SHORT,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Pan Li There will be a case like below for intrinsic and autovec combination vfadd RTZ <- intrinisc static rounding vfmadd <- autovec/autovec-opt The autovec generated vfmadd should take DYN mode, and the frm must be restored before the vfmadd insn. This patch would like to fix this issue by: * Add the frm operand to the vfmadd/vfmacc autovec/autovec-opt pattern. * Set the frm_mode attr to DYN. Thus, the frm flow when combine autovec and intrinsic should be. +------------ | frrm a5 | ... | fsrmi 4 | vfadd <- intrinsic static rounding. | ... | fsrm a5 | vfmadd <- autovec/autovec-opt | ... +------------ However, we leverage unspec instead of use to consume the FRM register because there are some restrictions from the combine pass. Some code path of try_combine may require the XVECLEN(pat, 0) == 2 for the recog_for_combine, and add new use will make the XVECLEN(pat, 0) == 3 and result in the vfwmacc optimization failure. For example, in the test widen-complicate-5.c and widen-8.c Finally, there will be other fma cases and they will be covered in the underlying patches. Signed-off-by: Pan Li Co-Authored-By: Ju-Zhe Zhong gcc/ChangeLog: * config/riscv/autovec-opt.md: Add FRM_REGNUM to vfmadd/vfmacc. * config/riscv/autovec.md: Ditto. * config/riscv/vector-iterators.md: Add UNSPEC_VFFMA. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-frm-autovec-1.c: New test. --- gcc/config/riscv/autovec-opt.md | 32 ++++--- gcc/config/riscv/autovec.md | 26 +++--- gcc/config/riscv/vector-iterators.md | 2 + .../rvv/base/float-point-frm-autovec-1.c | 88 +++++++++++++++++++ 4 files changed, 125 insertions(+), 23 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-1.c diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md index 99b609a99d9..4b07e80ad95 100644 --- a/gcc/config/riscv/autovec-opt.md +++ b/gcc/config/riscv/autovec-opt.md @@ -459,12 +459,14 @@ (define_insn_and_split "*pred_single_widen_mul" ;; vect__13.182_33 = .FMA (vect__11.180_35, vect__8.176_40, vect__4.172_45); (define_insn_and_split "*double_widen_fma" [(set (match_operand:VWEXTF 0 "register_operand") - (fma:VWEXTF - (float_extend:VWEXTF - (match_operand: 2 "register_operand")) - (float_extend:VWEXTF - (match_operand: 3 "register_operand")) - (match_operand:VWEXTF 1 "register_operand")))] + (unspec:VWEXTF + [(fma:VWEXTF + (float_extend:VWEXTF + (match_operand: 2 "register_operand")) + (float_extend:VWEXTF + (match_operand: 3 "register_operand")) + (match_operand:VWEXTF 1 "register_operand")) + (reg:SI FRM_REGNUM)] UNSPEC_VFFMA))] "TARGET_VECTOR && can_create_pseudo_p ()" "#" "&& 1" @@ -475,16 +477,19 @@ (define_insn_and_split "*double_widen_fma" DONE; } [(set_attr "type" "vfwmuladd") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))]) ;; This helps to match ext + fma. (define_insn_and_split "*single_widen_fma" [(set (match_operand:VWEXTF 0 "register_operand") - (fma:VWEXTF - (float_extend:VWEXTF - (match_operand: 2 "register_operand")) - (match_operand:VWEXTF 3 "register_operand") - (match_operand:VWEXTF 1 "register_operand")))] + (unspec:VWEXTF + [(fma:VWEXTF + (float_extend:VWEXTF + (match_operand: 2 "register_operand")) + (match_operand:VWEXTF 3 "register_operand") + (match_operand:VWEXTF 1 "register_operand")) + (reg:SI FRM_REGNUM)] UNSPEC_VFFMA))] "TARGET_VECTOR && can_create_pseudo_p ()" "#" "&& 1" @@ -501,7 +506,8 @@ (define_insn_and_split "*single_widen_fma" DONE; } [(set_attr "type" "vfwmuladd") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))]) ;; ------------------------------------------------------------------------- ;; ---- [FP] VFWNMSAC diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index acca4c22b90..4894986d2a5 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -1126,22 +1126,27 @@ (define_insn_and_split "*fnma" (define_expand "fma4" [(parallel [(set (match_operand:VF 0 "register_operand") - (fma:VF - (match_operand:VF 1 "register_operand") - (match_operand:VF 2 "register_operand") - (match_operand:VF 3 "register_operand"))) + (unspec:VF + [(fma:VF + (match_operand:VF 1 "register_operand") + (match_operand:VF 2 "register_operand") + (match_operand:VF 3 "register_operand")) + (reg:SI FRM_REGNUM)] UNSPEC_VFFMA)) (clobber (match_dup 4))])] "TARGET_VECTOR" { operands[4] = gen_reg_rtx (Pmode); - }) + } + [(set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))]) (define_insn_and_split "*fma" [(set (match_operand:VF 0 "register_operand" "=vr, vr, ?&vr") - (fma:VF - (match_operand:VF 1 "register_operand" " %0, vr, vr") - (match_operand:VF 2 "register_operand" " vr, vr, vr") - (match_operand:VF 3 "register_operand" " vr, 0, vr"))) + (unspec:VF + [(fma:VF + (match_operand:VF 1 "register_operand" " %0, vr, vr") + (match_operand:VF 2 "register_operand" " vr, vr, vr") + (match_operand:VF 3 "register_operand" " vr, 0, vr")) + (reg:SI FRM_REGNUM)] UNSPEC_VFFMA)) (clobber (match_operand:P 4 "register_operand" "=r,r,r"))] "TARGET_VECTOR" "#" @@ -1155,7 +1160,8 @@ (define_insn_and_split "*fma" DONE; } [(set_attr "type" "vfmuladd") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))]) ;; ------------------------------------------------------------------------- ;; ---- [FP] VFNMSAC and VFNMSUB diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index 4023a038fe9..9b2fb135bdd 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -81,6 +81,8 @@ (define_c_enum "unspec" [ UNSPEC_VCOMPRESS UNSPEC_VLEFF UNSPEC_MODIFY_VL + + UNSPEC_VFFMA ]) (define_c_enum "unspecv" [ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-1.c new file mode 100644 index 00000000000..f4f17a306d5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-1.c @@ -0,0 +1,88 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax -ffast-math -mabi=lp64 -O3 -Wno-psabi" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "riscv_vector.h" + +/* +**test_1: +** ... +** frrm\t[axt][0-9]+ +** ... +** fsrmi\t1 +** ... +** vfsub\.vv\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +** fsrm\t[axt][0-9]+ +** ... +** vfmadd\.vv\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +** ret +*/ +void +test_1 (vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t *op_out, size_t vl, + double *in1, double *in2, double *out) +{ + *op_out = __riscv_vfsub_vv_f32m1_rm (op1, op2, 1, vl); + + for (int i = 0; i < 4; ++i) + out[i] += in1[i] * in2[i]; +} + +/* +**test_2: +** ... +** frrm\t[axt][0-9]+ +** ... +** fsrmi\t1 +** ... +** vfsub\.vv\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +** fsrm\t[axt][0-9]+ +** ... +** vfmadd\.vv\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +** fsrmi\t4 +** ... +** vfsub\.vv\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +** fsrm\t[axt][0-9]+ +** ... +** ret +*/ +void +test_2 (vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t *op_out, size_t vl, + double *in1, double *in2, double *out) +{ + op2 = __riscv_vfsub_vv_f32m1_rm (op1, op2, 1, vl); + + for (int i = 0; i < 4; ++i) + out[i] = out[i] * in1[i] + in2[i]; + + *op_out = __riscv_vfsub_vv_f32m1_rm (op1, op2, 4, vl); +} + +/* +**test_3: +** ... +** frrm\t[axt][0-9]+ +** ... +** vfmadd\.vv\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +** fsrmi\t4 +** ... +** vfsub\.vv\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +** fsrm\t[axt][0-9]+ +** ... +** ret +*/ +void +test_3 (vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t *op_out, size_t vl, + double *in1, double *in2, double *in3, double *out) +{ + for (int i = 0; i < 4; ++i) + out[i] = in1[i] + in2[i] * out[i]; + + *op_out = __riscv_vfsub_vv_f32m1_rm (op1, op2, 4, vl); +} -- 2.34.1