From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.88]) by sourceware.org (Postfix) with ESMTPS id B2ABA3858C53 for ; Thu, 24 Aug 2023 07:13:14 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B2ABA3858C53 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1692861194; x=1724397194; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=KAWl9qlJQglCS8bmpQL9KcsnivfJ3NHQO6ghlAtr7zs=; b=GOau7hrAuz2NCZ10Z8VWu5u+/c7gsiEHT/8E4mv446lbdM/S2zlA/g7i MZExpIse74RsU1oMIdnTiFnnd8RejqLpohKcwIKt93/JkwSVPXlTx1bCT JV2zktrfaPdel24fsMSU2JkyAfvjMVAEfnHT633R0UWCw4/U3P47HczPU +3GB4IPVQT1gbrg0OHtpcOk7PG3KNmmg6LR11ur4N3rk0kK9JwAX9OJ0H Jt37CvVF+u7ZIGmU2H/D070HfqZ2jIFeKMaQs0s3GzJkZ0d+x4Mb9Eag9 PagDIuuba8YSznxDLj6GHXwBGSEjwyP5RLHqh3H248/dpaW+YkCo6ICD1 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10811"; a="405363569" X-IronPort-AV: E=Sophos;i="6.01,195,1684825200"; d="scan'208";a="405363569" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Aug 2023 00:11:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10811"; a="713856195" X-IronPort-AV: E=Sophos;i="6.01,195,1684825200"; d="scan'208";a="713856195" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by orsmga006.jf.intel.com with ESMTP; 24 Aug 2023 00:11:07 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id A364C100810A; Thu, 24 Aug 2023 15:11:06 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Support rounding mode for VFMSAC/VFMSUB autovec Date: Thu, 24 Aug 2023 15:11:04 +0800 Message-Id: <20230824071104.298243-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_ASCII_DIVIDERS,KAM_SHORT,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Pan Li There will be a case like below for intrinsic and autovec combination. vfadd RTZ <- intrinisc static rounding vfmsub <- autovec/autovec-opt The autovec generated vfmsub should take DYN mode, and the frm must be restored before the vfmsub insn. This patch would like to fix this issue by: * Add the frm operand to the autovec/autovec-opt pattern. * Set the frm_mode attr to DYN. Thus, the frm flow when combine autovec and intrinsic should be. +------------ | frrm a5 | ... | fsrmi 4 | vfadd <- intrinsic static rounding. | ... | fsrm a5 | vfmsub <- autovec/autovec-opt | ... +------------ Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/autovec-opt.md: Add FRM_REGNUM to vfmsac/vfmsub * config/riscv/autovec.md: Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c: New test. --- gcc/config/riscv/autovec-opt.md | 36 ++++---- gcc/config/riscv/autovec.md | 30 ++++--- .../rvv/base/float-point-frm-autovec-2.c | 88 +++++++++++++++++++ 3 files changed, 127 insertions(+), 27 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md index 4b07e80ad95..732a51edacd 100644 --- a/gcc/config/riscv/autovec-opt.md +++ b/gcc/config/riscv/autovec-opt.md @@ -583,13 +583,15 @@ (define_insn_and_split "*single_widen_fnma" ;; vect__13.182_33 = .FMS (vect__11.180_35, vect__8.176_40, vect__4.172_45); (define_insn_and_split "*double_widen_fms" [(set (match_operand:VWEXTF 0 "register_operand") - (fma:VWEXTF - (float_extend:VWEXTF - (match_operand: 2 "register_operand")) - (float_extend:VWEXTF - (match_operand: 3 "register_operand")) - (neg:VWEXTF - (match_operand:VWEXTF 1 "register_operand"))))] + (unspec:VWEXTF + [(fma:VWEXTF + (float_extend:VWEXTF + (match_operand: 2 "register_operand")) + (float_extend:VWEXTF + (match_operand: 3 "register_operand")) + (neg:VWEXTF + (match_operand:VWEXTF 1 "register_operand"))) + (reg:SI FRM_REGNUM)] UNSPEC_VFFMA))] "TARGET_VECTOR && can_create_pseudo_p ()" "#" "&& 1" @@ -600,17 +602,20 @@ (define_insn_and_split "*double_widen_fms" DONE; } [(set_attr "type" "vfwmuladd") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))]) ;; This helps to match ext + fms. (define_insn_and_split "*single_widen_fms" [(set (match_operand:VWEXTF 0 "register_operand") - (fma:VWEXTF - (float_extend:VWEXTF - (match_operand: 2 "register_operand")) - (match_operand:VWEXTF 3 "register_operand") - (neg:VWEXTF - (match_operand:VWEXTF 1 "register_operand"))))] + (unspec:VWEXTF + [(fma:VWEXTF + (float_extend:VWEXTF + (match_operand: 2 "register_operand")) + (match_operand:VWEXTF 3 "register_operand") + (neg:VWEXTF + (match_operand:VWEXTF 1 "register_operand"))) + (reg:SI FRM_REGNUM)] UNSPEC_VFFMA))] "TARGET_VECTOR && can_create_pseudo_p ()" "#" "&& 1" @@ -627,7 +632,8 @@ (define_insn_and_split "*single_widen_fms" DONE; } [(set_attr "type" "vfwmuladd") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))]) ;; ------------------------------------------------------------------------- ;; ---- [FP] VFWNMACC diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 4894986d2a5..d9f1a10eb66 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -1218,24 +1218,29 @@ (define_insn_and_split "*fnma" (define_expand "fms4" [(parallel [(set (match_operand:VF 0 "register_operand") - (fma:VF - (match_operand:VF 1 "register_operand") - (match_operand:VF 2 "register_operand") - (neg:VF - (match_operand:VF 3 "register_operand")))) + (unspec:VF + [(fma:VF + (match_operand:VF 1 "register_operand") + (match_operand:VF 2 "register_operand") + (neg:VF + (match_operand:VF 3 "register_operand"))) + (reg:SI FRM_REGNUM)] UNSPEC_VFFMA)) (clobber (match_dup 4))])] "TARGET_VECTOR" { operands[4] = gen_reg_rtx (Pmode); - }) + } + [(set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))]) (define_insn_and_split "*fms" [(set (match_operand:VF 0 "register_operand" "=vr, vr, ?&vr") - (fma:VF - (match_operand:VF 1 "register_operand" " %0, vr, vr") - (match_operand:VF 2 "register_operand" " vr, vr, vr") - (neg:VF - (match_operand:VF 3 "register_operand" " vr, 0, vr")))) + (unspec:VF + [(fma:VF + (match_operand:VF 1 "register_operand" " %0, vr, vr") + (match_operand:VF 2 "register_operand" " vr, vr, vr") + (neg:VF + (match_operand:VF 3 "register_operand" " vr, 0, vr"))) + (reg:SI FRM_REGNUM)] UNSPEC_VFFMA)) (clobber (match_operand:P 4 "register_operand" "=r,r,r"))] "TARGET_VECTOR" "#" @@ -1249,7 +1254,8 @@ (define_insn_and_split "*fms" DONE; } [(set_attr "type" "vfmuladd") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))]) ;; ------------------------------------------------------------------------- ;; ---- [FP] VFMSAC and VFMSUB diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c new file mode 100644 index 00000000000..77d0f5ef773 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c @@ -0,0 +1,88 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax -ffast-math -mabi=lp64 -O3 -Wno-psabi" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "riscv_vector.h" + +/* +**test_1: +** ... +** frrm\t[axt][0-9]+ +** ... +** fsrmi\t1 +** ... +** vfadd\.vv\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +** fsrm\t[axt][0-9]+ +** ... +** vfmsub\.vv\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +** ret +*/ +void +test_1 (vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t *op_out, size_t vl, + double *in1, double *in2, double *out) +{ + *op_out = __riscv_vfadd_vv_f32m1_rm (op1, op2, 1, vl); + + for (int i = 0; i < vl; ++i) + out[i] = in1[i] * in2[i] - out[i]; +} + +/* +**test_2: +** ... +** frrm\t[axt][0-9]+ +** ... +** fsrmi\t1 +** ... +** vfadd\.vv\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +** fsrm\t[axt][0-9]+ +** ... +** vfmsub\.vv\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +** fsrmi\t4 +** ... +** vfadd\.vv\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +** fsrm\t[axt][0-9]+ +** ... +** ret +*/ +void +test_2 (vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t *op_out, size_t vl, + double *in1, double *in2, double *out) +{ + op2 = __riscv_vfadd_vv_f32m1_rm (op1, op2, 1, vl); + + for (int i = 0; i < vl; ++i) + out[i] = out[i] * in1[i] - in2[i]; + + *op_out = __riscv_vfadd_vv_f32m1_rm (op1, op2, 4, vl); +} + +/* +**test_3: +** ... +** frrm\t[axt][0-9]+ +** ... +** vfmsub\.vv\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +** fsrmi\t4 +** ... +** vfadd\.vv\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +** fsrm\t[axt][0-9]+ +** ... +** ret +*/ +void +test_3 (vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t *op_out, size_t vl, + double *in1, double *in2, double *in3, double *out) +{ + for (int i = 0; i < vl; ++i) + out[i] = in2[i] * out[i] - in1[i]; + + *op_out = __riscv_vfadd_vv_f32m1_rm (op1, op2, 4, vl); +} -- 2.34.1