From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.43]) by sourceware.org (Postfix) with ESMTPS id 99C173858C53 for ; Thu, 24 Aug 2023 09:34:52 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 99C173858C53 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1692869692; x=1724405692; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=+xi67slCbl5P1FDNLakDdXCjOpB36d71ghhGzIfRURE=; b=NLae5+3Ryw9H7etCdhDsbCW2tgBJ3EEGtFr2Ms4+NMwyz2EtyT1ZO6bQ a0dYsdKuoGCAAACmvK7d0+M5xBZUIZ6vfwwr4xUtpayhKrva4Qp9IwQVH 6M5zpJSNyMpCCsy1Yt9kIDzBCYAXQlgItWrSRNY3RlLRycWgRcjstia3v snraO9A0rjePv2ZMeilvUBq2lIJs123eDOTvbxponGJszAgRHqfvD3Ouz ZbDeC8hwaHqfm3HmyXJ7BNJqNLilIH6niWFf028HeJsSID8Tcbid2D+Ap GoMQptvOpd7KFZVXN8Uskj05BE8ApCNK937Q043dnOPm1/4ihh8ogH5PV A==; X-IronPort-AV: E=McAfee;i="6600,9927,10811"; a="460747989" X-IronPort-AV: E=Sophos;i="6.01,195,1684825200"; d="scan'208";a="460747989" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Aug 2023 02:34:51 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10811"; a="772042426" X-IronPort-AV: E=Sophos;i="6.01,195,1684825200"; d="scan'208";a="772042426" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga001.jf.intel.com with ESMTP; 24 Aug 2023 02:34:48 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 697A11007814; Thu, 24 Aug 2023 17:34:47 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Support rounding mode for VFNMSAC/VFNMSUB autovec Date: Thu, 24 Aug 2023 17:34:46 +0800 Message-Id: <20230824093446.651760-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-10.8 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_ASCII_DIVIDERS,KAM_SHORT,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Pan Li There will be a case like below for intrinsic and autovec combination. vfadd RTZ <- intrinisc static rounding vfnmsub <- autovec/autovec-opt The autovec generated vfnmsub should take DYN mode, and the frm must be restored before the vfnmsub insn. This patch would like to fix this issue by: * Add the frm operand to the autovec/autovec-opt pattern. * Set the frm_mode attr to DYN. Thus, the frm flow when combine autovec and intrinsic should be. +------------ | frrm a5 | ... | fsrmi 4 | vfadd <- intrinsic static rounding. | ... | fsrm a5 | vfnmsub <- autovec/autovec-opt | ... +------------ Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/autovec-opt.md: Add FRM_REGNUM to vfnmsac/vfnmsub * config/riscv/autovec.md: Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-frm-autovec-3.c: New test. --- gcc/config/riscv/autovec-opt.md | 34 ++++--- gcc/config/riscv/autovec.md | 30 ++++--- .../rvv/base/float-point-frm-autovec-3.c | 88 +++++++++++++++++++ 3 files changed, 126 insertions(+), 26 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-3.c diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md index 732a51edacd..54ca6df721c 100644 --- a/gcc/config/riscv/autovec-opt.md +++ b/gcc/config/riscv/autovec-opt.md @@ -523,13 +523,15 @@ (define_insn_and_split "*single_widen_fma" ;; vect__13.182_33 = .FNMA (vect__11.180_35, vect__8.176_40, vect__4.172_45); (define_insn_and_split "*double_widen_fnma" [(set (match_operand:VWEXTF 0 "register_operand") - (fma:VWEXTF - (neg:VWEXTF + (unspec:VWEXTF + [(fma:VWEXTF + (neg:VWEXTF + (float_extend:VWEXTF + (match_operand: 2 "register_operand"))) (float_extend:VWEXTF - (match_operand: 2 "register_operand"))) - (float_extend:VWEXTF - (match_operand: 3 "register_operand")) - (match_operand:VWEXTF 1 "register_operand")))] + (match_operand: 3 "register_operand")) + (match_operand:VWEXTF 1 "register_operand")) + (reg:SI FRM_REGNUM)] UNSPEC_VFFMA))] "TARGET_VECTOR && can_create_pseudo_p ()" "#" "&& 1" @@ -540,17 +542,20 @@ (define_insn_and_split "*double_widen_fnma" DONE; } [(set_attr "type" "vfwmuladd") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))]) ;; This helps to match ext + fnma. (define_insn_and_split "*single_widen_fnma" [(set (match_operand:VWEXTF 0 "register_operand") - (fma:VWEXTF - (neg:VWEXTF - (float_extend:VWEXTF - (match_operand: 2 "register_operand"))) - (match_operand:VWEXTF 3 "register_operand") - (match_operand:VWEXTF 1 "register_operand")))] + (unspec:VWEXTF + [(fma:VWEXTF + (neg:VWEXTF + (float_extend:VWEXTF + (match_operand: 2 "register_operand"))) + (match_operand:VWEXTF 3 "register_operand") + (match_operand:VWEXTF 1 "register_operand")) + (reg:SI FRM_REGNUM)] UNSPEC_VFFMA))] "TARGET_VECTOR && can_create_pseudo_p ()" "#" "&& 1" @@ -567,7 +572,8 @@ (define_insn_and_split "*single_widen_fnma" DONE; } [(set_attr "type" "vfwmuladd") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))]) ;; ------------------------------------------------------------------------- ;; ---- [FP] VFWMSAC diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 0c1c546817a..28396c6175d 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -1174,24 +1174,29 @@ (define_insn_and_split "*fma" (define_expand "fnma4" [(parallel [(set (match_operand:VF 0 "register_operand") - (fma:VF - (neg:VF - (match_operand:VF 1 "register_operand")) - (match_operand:VF 2 "register_operand") - (match_operand:VF 3 "register_operand"))) + (unspec:VF + [(fma:VF + (neg:VF + (match_operand:VF 1 "register_operand")) + (match_operand:VF 2 "register_operand") + (match_operand:VF 3 "register_operand")) + (reg:SI FRM_REGNUM)] UNSPEC_VFFMA)) (clobber (match_dup 4))])] "TARGET_VECTOR" { operands[4] = gen_reg_rtx (Pmode); - }) + } + [(set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))]) (define_insn_and_split "*fnma" [(set (match_operand:VF 0 "register_operand" "=vr, vr, ?&vr") - (fma:VF - (neg:VF - (match_operand:VF 1 "register_operand" " %0, vr, vr")) - (match_operand:VF 2 "register_operand" " vr, vr, vr") - (match_operand:VF 3 "register_operand" " vr, 0, vr"))) + (unspec:VF + [(fma:VF + (neg:VF + (match_operand:VF 1 "register_operand" " %0, vr, vr")) + (match_operand:VF 2 "register_operand" " vr, vr, vr") + (match_operand:VF 3 "register_operand" " vr, 0, vr")) + (reg:SI FRM_REGNUM)] UNSPEC_VFFMA)) (clobber (match_operand:P 4 "register_operand" "=r,r,r"))] "TARGET_VECTOR" "#" @@ -1205,7 +1210,8 @@ (define_insn_and_split "*fnma" DONE; } [(set_attr "type" "vfmuladd") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))]) ;; ------------------------------------------------------------------------- ;; ---- [FP] VFMSAC and VFMSUB diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-3.c new file mode 100644 index 00000000000..abedfc1b8fb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-3.c @@ -0,0 +1,88 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax -ffast-math -mabi=lp64 -O3 -Wno-psabi" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "riscv_vector.h" + +/* +**test_1: +** ... +** frrm\t[axt][0-9]+ +** ... +** fsrmi\t1 +** ... +** vfadd\.vv\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +** fsrm\t[axt][0-9]+ +** ... +** vfnmsub\.vv\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +** ret +*/ +void +test_1 (vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t *op_out, size_t vl, + double *in1, double *in2, double *out) +{ + *op_out = __riscv_vfadd_vv_f32m1_rm (op1, op2, 1, vl); + + for (int i = 0; i < vl; ++i) + out[i] = - in1[i] * in2[i] + out[i]; +} + +/* +**test_2: +** ... +** frrm\t[axt][0-9]+ +** ... +** fsrmi\t1 +** ... +** vfadd\.vv\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +** fsrm\t[axt][0-9]+ +** ... +** vfnmsub\.vv\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +** fsrmi\t4 +** ... +** vfadd\.vv\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +** fsrm\t[axt][0-9]+ +** ... +** ret +*/ +void +test_2 (vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t *op_out, size_t vl, + double *in1, double *in2, double *out) +{ + op2 = __riscv_vfadd_vv_f32m1_rm (op1, op2, 1, vl); + + for (int i = 0; i < vl; ++i) + out[i] = - out[i] * in1[i] + in2[i]; + + *op_out = __riscv_vfadd_vv_f32m1_rm (op1, op2, 4, vl); +} + +/* +**test_3: +** ... +** frrm\t[axt][0-9]+ +** ... +** vfnmsub\.vv\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +** fsrmi\t4 +** ... +** vfadd\.vv\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +** fsrm\t[axt][0-9]+ +** ... +** ret +*/ +void +test_3 (vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t *op_out, size_t vl, + double *in1, double *in2, double *in3, double *out) +{ + for (int i = 0; i < vl; ++i) + out[i] = - in2[i] * out[i] + in1[i]; + + *op_out = __riscv_vfadd_vv_f32m1_rm (op1, op2, 4, vl); +} -- 2.34.1