From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id 8C5673858C53 for ; Fri, 25 Aug 2023 09:32:57 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8C5673858C53 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.20.4.107]) by gateway (Coremail) with SMTP id _____8Dxl+hEdehkXMobAA--.20660S3; Fri, 25 Aug 2023 17:32:53 +0800 (CST) Received: from loongson-pc.loongson.cn (unknown [10.20.4.107]) by localhost.localdomain (Coremail) with SMTP id AQAAf8BxB81BdehkukpjAA--.37635S2; Fri, 25 Aug 2023 17:32:51 +0800 (CST) From: Lulu Cheng To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, i@xen0n.name, xuchenghua@loongson.cn, Lulu Cheng Subject: [PATCH v2] LoongArch: Remove redundant sign extension instructions caused by SLT instructions. Date: Fri, 25 Aug 2023 17:31:57 +0800 Message-Id: <20230825093156.14808-1-chenglulu@loongson.cn> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CM-TRANSID:AQAAf8BxB81BdehkukpjAA--.37635S2 X-CM-SenderInfo: xfkh0wpoxo3qxorr0wxvrqhubq/ X-Coremail-Antispam: 1Uk129KBj93XoWxWrWUGF45ury3JFWxCrW8Xwc_yoW7Jr1kpr WxCw1a9r4kJas3A3W8J3y8Zry7Gr4fGF4SgFyftrWIkw43JryDWw1FyrySvFy5K3yFqr47 Xr4kZa13Xa42k3gCm3ZEXasCq-sJn29KB7ZKAUJUUUU5529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUyEb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_ GcCE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqjxCEc2xF0cIa020Ex4CE44I27wAqx4 xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_Jrv_JF1lYx0Ex4A2jsIE14v2 6r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwCF04k20xvY0x0EwI xGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480 Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_JF0_Jw1lIxkGc2Ij64vIr41lIxAIcVC0I7 IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Jr0_Gr1lIxAIcVCF04k2 6cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxV AFwI0_Jr0_GrUvcSsGvfC2KfnxnUUI43ZEXa7IU1QVy3UUUUU== X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_SHORT,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: v1 -> v2: 1. Modify description information Since the SLT instruction does not distinguish between 64-bit operations and 32-bit operations under the 64-bit LoongArch architecture, if the operand of slt is SImode, the sign extension of the operand needs to be displayed. But similar to the test case below, the sign extension is redundant: extern int src1, src2, src3; int test (void) { int data1 = src1 + src2; int data2 = src1 + src3; return data1 > data2 ? data1 : data2; } Assembly code before optimization: ... add.w $r4,$r4,$r14 add.w $r13,$r13,$r14 slli.w $r12,$r4,0 slli.w $r14,$r13,0 slt $r12,$r12,$r14 masknez $r4,$r4,$r12 maskeqz $r12,$r13,$r12 or $r4,$r4,$r12 slli.w $r4,$r4,0 ... After optimization: ... add.w $r12,$r12,$r14 add.w $r13,$r13,$r14 slt $r4,$r12,$r13 masknez $r12,$r12,$r4 maskeqz $r4,$r13,$r4 or $r4,$r12,$r4 ... Similar to this test example, the two operands of SLT are obtained by the addition operation, and add.w implicitly sign-extends, so the two operands of SLT do not require sign-extend. gcc/ChangeLog: * config/loongarch/loongarch.cc (loongarch_expand_conditional_move): Optimize the function implementation. gcc/testsuite/ChangeLog: * gcc.target/loongarch/slt-sign-extend.c: New test. --- gcc/config/loongarch/loongarch.cc | 53 +++++++++++++++++-- .../gcc.target/loongarch/slt-sign-extend.c | 14 +++++ 2 files changed, 63 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.target/loongarch/slt-sign-extend.c diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc index 86d58784113..1905599b9e8 100644 --- a/gcc/config/loongarch/loongarch.cc +++ b/gcc/config/loongarch/loongarch.cc @@ -4384,14 +4384,30 @@ loongarch_expand_conditional_move (rtx *operands) enum rtx_code code = GET_CODE (operands[1]); rtx op0 = XEXP (operands[1], 0); rtx op1 = XEXP (operands[1], 1); + rtx op0_extend = op0; + rtx op1_extend = op1; + + /* Record whether operands[2] and operands[3] modes are promoted to word_mode. */ + bool promote_p = false; + machine_mode mode = GET_MODE (operands[0]); if (FLOAT_MODE_P (GET_MODE (op1))) loongarch_emit_float_compare (&code, &op0, &op1); else { + if ((REGNO (op0) == REGNO (operands[2]) + || (REGNO (op1) == REGNO (operands[3]) && (op1 != const0_rtx))) + && (GET_MODE_SIZE (GET_MODE (op0)) < word_mode)) + { + mode = word_mode; + promote_p = true; + } + loongarch_extend_comparands (code, &op0, &op1); op0 = force_reg (word_mode, op0); + op0_extend = op0; + op1_extend = force_reg (word_mode, op1); if (code == EQ || code == NE) { @@ -4418,23 +4434,52 @@ loongarch_expand_conditional_move (rtx *operands) && register_operand (operands[2], VOIDmode) && register_operand (operands[3], VOIDmode)) { - machine_mode mode = GET_MODE (operands[0]); + rtx op2 = operands[2]; + rtx op3 = operands[3]; + + if (promote_p) + { + if (REGNO (XEXP (operands[1], 0)) == REGNO (operands[2])) + op2 = op0_extend; + else + { + loongarch_extend_comparands (code, &op2, &const0_rtx); + op2 = force_reg (mode, op2); + } + + if (REGNO (XEXP (operands[1], 1)) == REGNO (operands[3])) + op3 = op1_extend; + else + { + loongarch_extend_comparands (code, &op3, &const0_rtx); + op3 = force_reg (mode, op3); + } + } + rtx temp = gen_reg_rtx (mode); rtx temp2 = gen_reg_rtx (mode); emit_insn (gen_rtx_SET (temp, gen_rtx_IF_THEN_ELSE (mode, cond, - operands[2], const0_rtx))); + op2, const0_rtx))); /* Flip the test for the second operand. */ cond = gen_rtx_fmt_ee ((code == EQ) ? NE : EQ, GET_MODE (op0), op0, op1); emit_insn (gen_rtx_SET (temp2, gen_rtx_IF_THEN_ELSE (mode, cond, - operands[3], const0_rtx))); + op3, const0_rtx))); /* Merge the two results, at least one is guaranteed to be zero. */ - emit_insn (gen_rtx_SET (operands[0], gen_rtx_IOR (mode, temp, temp2))); + if (promote_p) + { + rtx temp3 = gen_reg_rtx (mode); + emit_insn (gen_rtx_SET (temp3, gen_rtx_IOR (mode, temp, temp2))); + temp3 = gen_lowpart (GET_MODE (operands[0]), temp3); + loongarch_emit_move (operands[0], temp3); + } + else + emit_insn (gen_rtx_SET (operands[0], gen_rtx_IOR (mode, temp, temp2))); } else emit_insn (gen_rtx_SET (operands[0], diff --git a/gcc/testsuite/gcc.target/loongarch/slt-sign-extend.c b/gcc/testsuite/gcc.target/loongarch/slt-sign-extend.c new file mode 100644 index 00000000000..ea6b28b7c45 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/slt-sign-extend.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mabi=lp64d -O2" } */ +/* { dg-final { scan-assembler-not "slli.w" } } */ + +extern int src1, src2, src3; + +int +test (void) +{ + int data1 = src1 + src2; + int data2 = src1 + src3; + + return data1 > data2 ? data1 : data2; +} -- 2.31.1