[PATCH] RISC-V: Remove movmisalign pattern for VLA modes

[Juzhe-Zhong <juzhe.zhong@rivai.ai>]

This patch fixed this bunch of failures in "vect" testsuite:
FAIL: gcc.dg/vect/pr63341-1.c -flto -ffat-lto-objects execution test
FAIL: gcc.dg/vect/pr63341-1.c execution test
FAIL: gcc.dg/vect/pr63341-2.c -flto -ffat-lto-objects execution test
FAIL: gcc.dg/vect/pr63341-2.c execution test
FAIL: gcc.dg/vect/pr94994.c -flto -ffat-lto-objects execution test
FAIL: gcc.dg/vect/pr94994.c execution test
FAIL: gcc.dg/vect/vect-align-1.c -flto -ffat-lto-objects execution test
FAIL: gcc.dg/vect/vect-align-1.c execution test
FAIL: gcc.dg/vect/vect-align-2.c -flto -ffat-lto-objects execution test
FAIL: gcc.dg/vect/vect-align-2.c execution test

Spike report:
z  0000000000000000 ra 00000000000100f4 sp 0000003ffffffb30 gp 0000000000012cc8
tp 0000000000000000 t0 00000000000102d4 t1 000000000000000f t2 0000000000000000
s0 0000000000000000 s1 0000000000000000 a0 00000000000101a6 a1 0000000000000008
a2 0000000000000010 a3 0000000000012401 a4 0000000000012480 a5 0000000000000020
a6 000000000000001f a7 00000000000000d6 s2 0000000000000000 s3 0000000000000000
s4 0000000000000000 s5 0000000000000000 s6 0000000000000000 s7 0000000000000000
s8 0000000000000000 s9 0000000000000000 sA 0000000000000000 sB 0000000000000000
t3 0000000000000000 t4 0000000000000000 t5 0000000000000000 t6 0000000000000000
pc 00000000000101ec va/inst 000000000206dc07 sr 8000000200006620
Load access fault!

(spike)
core   0: 0x0000000000010204 (0x02065087) vle16.v v1, (a2)
core   0: exception trap_load_address_misaligned, epc 0x0000000000010204
core   0:           tval 0x0000000000012c81
(spike) reg 0 a2
0x0000000000012c81

According to RVV ISA, we couldn't use "vle16.v" if the address is byte align.

Such issue is caused by this GIMPLE IR:

vect__1.15_17 = .MASK_LEN_LOAD (vectp_t.13_15, 8B, { -1, ... }, _24, 0);

For partial vectorization, the alignment is "8B" byte align here is incorrect here.

After this patch, the vectorization failed:

sll     a5,a4,0x1
add     a5,a5,a1
lhu     a3,64(a5)
lbu     a5,66(a5)
addw    a4,a4,1
srl     a3,a3,0x8
sll     a5,a5,0x8
or      a5,a5,a3
sh      a5,0(a2)
add     a2,a2,2
bne     a4,a0,101f8 <foo+0x14>

I will enable auto-vectorization in another approach in the next following patch.

gcc/ChangeLog:

	* config/riscv/autovec.md (movmisalign<mode>): Delete.

---
 gcc/config/riscv/autovec.md | 11 -----------
 1 file changed, 11 deletions(-)

diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 20ab0693b98..07e46d6ce49 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -46,17 +46,6 @@
   DONE;
 })
 
-(define_expand "movmisalign<mode>"
-  [(set (match_operand:V 0 "nonimmediate_operand")
-	(match_operand:V 1 "general_operand"))]
-  "TARGET_VECTOR"
-  {
-    /* Equivalent to a normal move for our purpooses.  */
-    emit_move_insn (operands[0], operands[1]);
-    DONE;
-  }
-)
-
 ;; =========================================================================
 ;; == Gather Load
 ;; =========================================================================
-- 
2.36.3